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data sheet preliminary information n8973dsd june 15, 1999 preliminary information this document contains information on a product under development. the parametric information contains target parameters that are subject to change. rs8973 single-chip sdsl/hdsl transceiver the rs8973 is a full-duplex 2b1q transceiver based on conexants hdsl technology, with a built-in frequency synthesizer to support variable rate sdsl applications. it offers 2320 kbps operation, low power consumption, and pin-for-pin compatibility with bt8970 and bt8960. the rs8973 is a highly integrated device that includes all of the active circuitry needed for a complete 2b1q transceiver. in the receive portion of the device, a variable gain amplifier optimizes the signal level according to the dynamic range of the analog-to-digital converter. once the signal is digitized, sophisticated adaptive echo cancellation, equalization, and detection dsp algorithms reproduce the originally transmitted far-end signal. in the transmitter, the transmit source and scrambler operation are programmable through the microcomputer interface. a highly linear digital-to-analog converter with programmable gain sets the transmission power for optimal performance. a pulse shaping filter and a low-distortion line driver generate the signal characteristics needed to drive a large range of subscriber lines at low distortion. the integrated frequency synthesizer is ideal for variable rate sdsl applications. the rs8973 can be programmed to operate at data rates ranging from 144 kbps to 2320 kbps, using a single crystal as a reference clock source. the rs8973 is fully compliant with standards for hdsl 2b1q transmission. key to variable rate applications, it can meet the psd, output power, and pulse shape requirements, as specified in etsi ts 101 135 (formerly etr 152 ) with the same support circuit. therefore, a single design using the rs8973 can be configured through a simple software command to operate at either 784, 1168, or 2320 kbps and will still meet these etsi requirements. no hardware changes are required. startup and performance monitoring operations are controlled through the microprocessor interface. c-language source code supporting these operations is supplied under a no-fee license agreement from conexant. the rs8973 includes a glueless interface to both intel and motorola microprocessors. functional block diagram analog receive mpu bus analog transmit variable gain amplifier microcomputer interface line driver pulse shaping filter analog- to-digital converter digital signal processor framer/ channel unit interface recovered data and clock transmit data clock synthesizer program- mable gain dac 8973_001 distinguishing features ? supports data rates ranging from 144 kbps to 2320 kbps ? integrated frequency synthesizer ? meets etsi ts 101 135 (formerly etr 152) pulse template, output power and psd specifications at 784, 1168 and 2320 kbps data rates, using the same external support circuit ? meets ansi t1/e1.4/94-006 pulse template, output power and psd specifications at 784 kbps. ? pin-for-pin and software compatible with bt8970 and bt8960 ? supports automatic rate adaptation ? single-chip 2b1q transceiver solution ? low power consumption (under 685 mw at 784 kbps operation) ? glueless interface to motorola and intel processors ? flexible monitoring and control ? backwards compatible with bt8952, bt8960, and bt8970 software api commands ? zipstartup ? available for faster link establishment ? rs8953b companion sdsl/hdsl framers available ? jtag/ieee std 1149.1 compliant ? 100-pin pqfp package ? C40 c to +85 c operation applications ? variable rate data access systems ? data access concentrators ? e1 and t1 hdsl transport ? internet connectivity ? voice and/or data pair gain systems ? n 64 data transport ? isdn bri concentrators ? cellular base station data links ? campus modems
n8973dsd conexant preliminary information information provided by conexant systems, inc. (conexant) is believed to be accurate and reliable. however, no responsibility i s assumed by conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use . no license is granted by implication or otherwise under any patent rights of conexant other than for circuitry embodied in conexan t products. conexant reserves the right to change circuitry at any time without notice. this document is subject to change withou t notice. conexant and whats next in communications technologies are trademarks of conexant systems, inc. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. ? 1999 conexant systems, inc. printed in u.s.a. all rights reserved reader response: to improve the quality of our publications, we welcome your feedback. please send comments or suggestions via e-mail to conexant reader response@conexant.com . sorry, we can't answer your technical questions at this address. please contact your local conexant sales office or local field applications engineer if you have technical questions. ordering information model number package operating temperature RS8973EPF 100-pin plastic quad flat pack C40 c to +85 c
n8973dsd conexant iii preliminary information table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1.0 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 1 1.1 functional summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 transmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.2 receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.3 timing recovery and clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.4 microcomputer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.5 test and diagnostic interface (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3 regenerator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 transmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 symbol source selector/scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 variable gain digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 pulse-shaping filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.4 analog ct reconstruction filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.5 line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2 receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 variable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.2 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3 digital signal processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.3.1 digital front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.3.2 offset adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.3 dc level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.4 signal level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.5 overflow detection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.6 far-end level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.7 far-end level alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.4 impulse shortening filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
table of contents rs8973 single-chip sdsl/hdsl transceiver iv conexant n8973dsd preliminary information 2.2.5 echo canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.5.1 linear echo canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.5.2 nonlinear echo canceller (nec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.6 equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.6.1 digital automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.6.2 feed forward equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.6.3 error predictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.6.4 decision feedback equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.6.5 microcoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7 detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7.1 slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7.2 peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7.3 error signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7.4 scrambler module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.7.5 sync detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.7.6 detector meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3 timing recovery and clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1 timing recovery circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.2 crystal amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.3 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.4 channel unit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5 microcomputer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.1 source code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.2 microcomputer read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.2.1 ram access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.2.2 multiplexed address/data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.2.3 separated address/data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.3 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.5.5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.5.6 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.5.7 scratch pad memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.6 test and diagnostic interface (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
rs8973 table of contents single-chip sdsl/hdsl transceiver n8973dsd conexant v preliminary information 3.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 0x00global modes and status register (global_modes) . . . . . . . . . . . . . . . . . . . . . . . . 3-7 0x01serial monitor source select register (serial_monitor_source) . . . . . . . . . . . . . . . 3-8 0x02interrupt mask register low (mask_low_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 0x03interrupt mask register high (mask_high_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 0x04timer source register (timer_source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 0x05irq source register (irq_source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 0x06channel unit interface modes register (cu_interface_modes) . . . . . . . . . . . . . . 3-11 0x07receive phase select register (receive_phase_select) . . . . . . . . . . . . . . . . . . . . 3-12 0x08linear echo canceller modes register (linear_ec_modes) . . . . . . . . . . . . . . . . . 3-12 0x09nonlinear echo canceller modes register (nonlinear_ec_modes) . . . . . . . . . . . . 3-13 0x0adecision feedback equalizer modes register (dfe_modes) . . . . . . . . . . . . . . . . . 3-13 0x0btransmitter modes register (transmitter_modes) . . . . . . . . . . . . . . . . . . . . . . . 3-14 0x0ctimer restart register (timer_restart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 0x0dtimer enable register (timer_enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 0x0etimer continuous mode register (timer_continuous) . . . . . . . . . . . . . . . . . . . . . 3-16 0x0fmiscellaneous/test register (misc_test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 0x10, 0x11startup timer 1 interval register (sut1_low, sut1_high) . . . . . . . . . . . . . . 3-16 0x12, 0x13startup timer 2 interval register (sut2_low, sut2_high) . . . . . . . . . . . . . . 3-16 0x14, 0x15startup timer 3 interval register (sut3_low, sut3_high) . . . . . . . . . . . . . . 3-17 0x16, 0x17startup timer 4 interval register (sut4_low, sut4_high) . . . . . . . . . . . . . . 3-17 0x18, 0x19meter timer interval register (meter_low, meter_high) . . . . . . . . . . . . . . . 3-17 0x1a, 0x1bsnr alarm timer interval register (snr_timer_low, snr_timer_high) . . . . 3-17 0x1c, 0x1dgeneral purpose timer 3 interval register (t3_low, t3_high) . . . . . . . . . . 3-17 0x1e, 0x1fgeneral purpose timer 4 interval register (t4_low, t4_high) . . . . . . . . . . . 3-17 0x20clock frequency select register (clock_freq_select) . . . . . . . . . . . . . . . . . . . . . 3-18 0x21adc control register (adc_control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 0x22pll modes register (pll_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 0x23test register (test_reg23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 0x24, 0x25timing recovery pll phase offset register (pll_phase_offset_low, pll_phase_offset_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 0x26, 0x27receiver dc offset register (dc_offset_low, dc_offset_high) . . . . . . . . . . 3-20 0x28transmitter calibration register (tx_calibrate) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 0x29transmitter gain register (tx_gain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 0x2a, 0x2bnoise-level histogram threshold register (noise_histogram_th_low, noise_histogram_th_high) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 0x2c, 0x2derror predictor pause threshold register (ep_pause_th_low, ep_pause_th_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 0x2escrambler synchronization threshold register (scr_sync_th) . . . . . . . . . . . . . . 3-22 0x30, 0x31far-end high alarm threshold register (far_end_high_alarm_th_low, far_end_high_alarm_th_high) . . . . . . . . . . . . . . . . . . . . . 3-22
table of contents rs8973 single-chip sdsl/hdsl transceiver vi conexant n8973dsd preliminary information 0x32, 0x33far-end low alarm threshold register (far_end_low_alarm_th_low, far_end_low_alarm_th_high) . . . . . . . . . . . . . . . . . . . . . . 3-22 0x34, 0x35snr alarm threshold register (snr_alarm_th_low, snr_alarm_th_high) . . 3-22 0x36, 0x37cursor level register (cursor_level_low, cursor_level_high) . . . . . . . . . . . 3-22 0x38, 0x39dagc target register (dagc_target_low, dagc_target_high) . . . . . . . . . . . 3-22 0x3asymbol detector modes register (detector_modes) . . . . . . . . . . . . . . . . . . . . . . 3-23 0x3bpeak detector delay register (peak_detector_delay) . . . . . . . . . . . . . . . . . . . . . 3-24 0x3cdigital agc modes register (dagc_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 0x3dfeed forward equalizer modes register (ffe_modes) . . . . . . . . . . . . . . . . . . . . . 3-25 0x3eerror predictor modes register (ep_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 0x40, 0x41phase detector meter register (pdm_low, pdm_high) . . . . . . . . . . . . . . . . 3-26 0x42overflow meter register (overflow_meter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 0x44, 0x45dc level meter register (dc_meter_low, dc_meter_high) . . . . . . . . . . . . . 3-27 0x46, 0x47signal level meter register (slm_low, slm_high) . . . . . . . . . . . . . . . . . . . 3-27 0x48, 0x49far-end level meter register (felm_low, felm_high) . . . . . . . . . . . . . . . . . 3-27 0x4a, 0x4bnoise level histogram meter register (noise_histogram_low, noise_histogram_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 0x4c, 0x4dbit error rate meter register (ber_meter_low, ber_meter_high) . . . . . . . . 3-28 0x4esymbol histogram meter register (symbol_histogram) . . . . . . . . . . . . . . . . . . . 3-28 0x50, 0x51noise level meter register (nlm_low, nlm_high) . . . . . . . . . . . . . . . . . . . 3-29 0x5e, 0x5f pll frequency register (pll_frequency_low, pll_frequency_high) . . . . . . . 3-29 0x70lec read tap select register (linear_ec_tap_select_read) . . . . . . . . . . . . . . . . . 3-29 0x71lec write tap select register (linear_ec_tap_select_write) . . . . . . . . . . . . . . . . 3-29 0x72nec read tap select register (nonlinear_ec_tap_select_read) . . . . . . . . . . . . . . 3-30 0x73nec write tap select register (nonlinear_ec_tap_select_write) . . . . . . . . . . . . . 3-30 0x74dfe read tap select register (dfe_tap_select_read) . . . . . . . . . . . . . . . . . . . . . 3-30 0x75dfe write tap select register (dfe_tap_select_write) . . . . . . . . . . . . . . . . . . . . . 3-30 0x76scratch pad read tap select (sp_tap_select_read) . . . . . . . . . . . . . . . . . . . . . . . 3-31 0x77scratch pad write tap select (sp_tap_select_write) . . . . . . . . . . . . . . . . . . . . . . 3-31 0x78equalizer read select register (eq_add_read) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 0x79equalizer write select register (eq_add_write) . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 0x7aequalizer microcode read select register (eq_microcode_add_read) . . . . . . . . . 3-33 0x7bequalizer microcode write select register (eq_microcode_add_write) . . . . . . . . 3-33 0x7cC0x7faccess data register (access_data_byte3:0) . . . . . . . . . . . . . . . . . . . . . . 3-33 4.0 interconnection information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 transmission line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 compromise hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.2 impedance-matching resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.3 line transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2 dc blocking capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
rs8973 table of contents single-chip sdsl/hdsl transceiver n8973dsd conexant vii preliminary information 4.3 voltage reference and compensation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4 crystal/clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 5.0 electrical and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.5 channel unit interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.6 microcomputer interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.7 test and diagnostic interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.8 analog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.9 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.10 timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.11 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 appendix a: acronym list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1
table of contents rs8973 single-chip sdsl/hdsl transceiver viii conexant n8973dsd preliminary information
rs8973 list of figures single-chip sdsl/hdsl transceiver n8973dsd conexant ix preliminary information list of figures figure 1-1. hdsl t1/e1 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 figure 1-2. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 figure 1-3. pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-4. regenerator system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 11 figure 2-1. transmit section block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 figure 2-2. first-order echo cancellation using the variable gain amplifier . . . . . . . . . . . . . . . . . . . . . 2-5 figure 2-3. receiver digital signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 figure 2-4. digital front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 figure 2-5. timing recovery and clock interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 figure 2-6. serial sign-bit first mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 figure 2-7. parallel master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 figure 2-8. parallel slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 figure 4-1. line interface interconnection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-2. crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 figure 5-1. mclk timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-2. clock control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-3. channel unit interface timing, parallel master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-4. channel unit interface timing, parallel slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-5. channel unit interface timing, serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 8 figure 5-6. mci write timing, intel mode (motel = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-7. mci write timing, motorola mode (motel = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-8. mci read timing, intel mode (motel = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 5-9. mci read timing, motorola mode (motel = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 5-10. internal write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 figure 5-11. jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 figure 5-12. smon timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 figure 5-13. transmit pulse template for two- and three-pair systems; normalized pulse mask. . . . 5-18 figure 5-14. transmit pulse template for one-pair systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 figure 5-15. upper bound of the average psd of a 392 kbaud system . . . . . . . . . . . . . . . . . . . . . . . . 5-20 figure 5-16. upper bound of the average psd of a 584 kbaud system . . . . . . . . . . . . . . . . . . . . . . . . 5-20 figure 5-17. upper bound of the average psd of a 1160 kbaud system . . . . . . . . . . . . . . . . . . . . . . . 5-21 figure 5-18. transmitter test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 figure 5-19. standard output load (totem pole and three-state outputs) . . . . . . . . . . . . . . . . . . . . . 5-22 figure 5-20. open-drain output load (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 figure 5-21. input waveforms for timing tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 figure 5-22. output waveforms for timing tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -23 figure 5-23. output waveforms for three-state enable and disable tests . . . . . . . . . . . . . . . . . . . . . . 5-24 figure 5-24. 100-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
list of figures rs8973 single-chip sdsl/hdsl transceiver x conexant n8973dsd preliminary information
rs8973 list of tables single-chip sdsl/hdsl transceiver n8973dsd conexant xi preliminary information list of tables table 1-1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 table 1-2. hardware signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 table 2-1. symbol source selector/scrambler modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 table 2-2. four-level bit-to-symbol conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 table 2-3. two-level bit-to-symbol conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-4. two-level symbol-to-bit conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -11 table 2-5. four-level symbol-to-bit conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 table 2-6. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 table 2-7. jtag device identification register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 table 3-1. register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 table 3-2. address map of shared register fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32 table 4-1. compromise hybrid component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 table 4-2. antialias filter component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-3. line transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-4. line transformer application-specific specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-5. recommended line transformer suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-6. dc blocking capacitor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-7. compensation capacitor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-8. bias current resistor value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-9. crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 4-10. recommended crystal suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 5-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 table 5-2. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -2 table 5-3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-4. mclk timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 table 5-5. hclk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 table 5-6. qclk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-7. channel unit interface timing requirements, parallel master mode. . . . . . . . . . . . . . . . . . . 5-6 table 5-8. channel unit interface switching characteristics, parallel master mode. . . . . . . . . . . . . . . . 5-6 table 5-9. channel unit interface timing requirements, parallel slave mode . . . . . . . . . . . . . . . . . . . . 5-7 table 5-10. channel unit interface switching characteristics, parallel slave mode . . . . . . . . . . . . . . . . . 5-7 table 5-11. channel unit interface timing requirements, serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-12. channel unit interface switching characteristics, serial mode . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-13. microcomputer interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-14. microcomputer interface switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-15. test and diagnostic interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table 5-16. test and diagnostic interface switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table 5-17. receiver requirements and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 16 table 5-18. transmitter analog requirements and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 table 5-19. transmit pulse template for two- and three-pair systems . . . . . . . . . . . . . . . . . . . . . . . . 5-18 table 5-20. transmit pulse template for one-pair systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
list of tables rs8973 single-chip sdsl/hdsl transceiver xii conexant n8973dsd preliminary information
n8973dsd conexant 1-1 preliminary information 1 1.0 system overview 1.1 functional summary the rs8973 high-bit-rate digital subscriber line (hdsl) transceiver is an integral component of conexant's hdsl chipset. system performance of the chipset allows 2-pair t1, 1-pair e1, 2-pair e1, and 3-pair e1 transmission. with its built-in frequency synthesizer, it can easily be configured through software for variable rate symmetric dsl over single pair (sdsl) applications, using a single 10.24 mhz crystal/clock as reference. it can operate at data rates between 144 kbps and 2320 kbps. the major building blocks of a typical hdsl t1/e1 terminal are shown in figure 1-1 . figure 1-1. hdsl t1/e1 terminal t1/e1 receive line t1/e1 transmit line bt8370 t1/e1 framer and liu transformer and hybrid transformer and hybrid transformer and hybrid hdsl twisted pair hdsl twisted pair hdsl twisted pair rs8973 transceiver rs8973 transceiver rs8973 transceiver rs8953b/ bt8953a t1/e1 hdsl channel unit optional second, third pair 8973_002
1.0 system overview rs8973 1.1 functional summary single-chip sdsl/hdsl transceiver 1-2 conexant n8973dsd preliminary information the rs8973 comprises five major functions: a transmit section, a receive section, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. figure 1-2 details the connections within and between each of these functional blocks. figure 1-2. detailed block diagram motel timing recovery/ pll crystal amplifier diag- nostics jtag receive section microcomputer interface and system control transmit section tbclk ale cs rd/ds wr/r/w ad[7:0] irq rst txp txn rq[0]/bclk smon tms tdi tck tdo tq[1]/tdat tq[0] voltage reference generator pulse- shaping filter variable- gain dac line driver control and status registers timers microcomputer interface ready addr[7:0] rxp rxn rxbp rxbn muxed rq[1]/rdat rbclk hclk qclk xtali/mclk xtalo xout rbias vcomo vcomi vccap vrxp,vrxn vtxp,vtxn transmit channel unit interface symbol source/ scrambler clock synthesizer analog ct reconstruc- tion filter echo canceller vga adc digital front end equalizer detector receive channel unit interface is filter 8973_003
rs8973 1.0 system overview single-chip sdsl/hdsl transceiver 1.1 functional summary n8973dsd conexant 1-3 preliminary information 1.1.1 transmit section the source of transmitted symbols is programmable through the microcomputer interface. the primary choices include external 2b1q-encoded data presented to the tq[1,0]/tdat pins of the channel unit interface, internally looped-back receive symbols from the detector, or a constant all 1s source. the symbols are then optionally scrambled. isolated pulses can also be generated to support the testing of pulse templates. the digital symbols are transformed to an analog signal by means of the dac, which is highly linear to maximize the echo cancellation and detection properties of the signal. in addition, the transmit power level of the dac can be adjusted by means of the transmitter gain register [tx_gain; 0x29] to optimize performance. the transmitter calibration register [tx_calibrate; 0x28] contains the nominal setting for the transmitter gain, which is calibrated and hard-coded at the factory. the pulse-shaping filters, along with the analog continuous time (ct) reconstruction filter, then condition the signal to minimize crosstalk to adjacent subscriber lines. this filtering enables the output signal to meet requirements of etsi ts 101 135 (formerly etr 152) specifications for pulse shape, power spectral density and output power at 784 kbps, 1168 kbps, and 2320 kbps without any changes required to external components, including the line transformer. finally, the differential line driver provides the current driving capabilities and low-distortion characteristics needed to drive a large range of subscriber lines. 1.1.2 receive section the differential variable gain amplifier (vga) receives the data from the subscriber line. balancing inputs (rxbp, rxbn) are provided to accommodate first-order transmit echo cancellation through an external hybrid. the gain is programmable so that the dynamic range of the analog-to-digital converter (adc) can be utilized according to the attenuation of the subscriber line. digitized receive data is passed to the digital signal processor (dsp) portion of the rs8973. after dc offset cancellation, the impulse shortening (is) filter eliminates long tails caused by the line transformer. a replica of the transmit signal is subtracted from the total receive signal by a digital echo canceller. the resultant far-end signal is then conditioned by an equalization stage consisting of automatic gain control (agc), a feed-forward equalizer, a decision-feedback equalizer, and an error predictor. a mode-dependent detector is then used to recover the 2b1q-encoded data from the equalized signal. the channel unit interface then provides an optional descrambling function, followed by parallel or serial output of the sign, and magnitude bits on pins rq[1,0]/rdat. a number of meters are implemented within the receiver to provide average level indications at various points in the receive signal path. the receive section also performs remote unit clock recovery through an on-chip phase lock loop (pll) circuit.
1.0 system overview rs8973 1.1 functional summary single-chip sdsl/hdsl transceiver 1-4 conexant n8973dsd preliminary information 1.1.3 timing recovery and clock interface the clock interface includes a crystal amplifier and a clock synthesizer module to reduce the external components needed for clock generation. the crystal frequency should be 10.24 mhz. the clock synthesizer generates the required internal clock from this reference clock based on the data rate, as specified by the clock frequency select register [clk_select [7:0]; 0x20] and pll modes register [clk_select [9,8]; 0x22]. when configured as a remote unit, the pll module recovers the incoming data clock and outputs it on the qclk pin (on the bclk pin for serial mode operation). the hclk output, which is synchronized to the qclk signal, can be configured to cycle at 16, 32, or 64 times the symbol rate. 1.1.4 microcomputer interface the microcomputer interface (mci) provides access to a 256-byte address space within the transceiver. a combination of direct and indirect addressing methods are used to access all internal locations. the mci is designed to interface with both intel- and motorola-style processors with no additional glue logic. a motel control pin is provided to configure the bus interface control/handshake lines to conform to common motorola/intel conventions. a muxed control pin is provided to configure the bus interface address and data lines for multiplexed or independent data/address bus operation. little-endian data formatting (least significant byte of a multibyte word stored at the lowest byte-address location) is used in all cases, regardless of motel pin selection. a ready control pin is provided to support wait-state insertion. an interrupt request (irq ) output pin supports low-latency responses to time-critical events within the transceiver. eight 16-bit timers and 10 measurement meters are integrated into the transceiver. the timers support various metering functions within the receiver section and off-load the external microcomputer from complex timing operations associated with startup procedures. control and monitoring access to the timers and meters is provided through the mci. 1.1.5 test and diagnostic interface (jtag) the test and diagnostic interface comprises a test access port and a serial monitor output (smon). the test access port conforms to ieee std 1149.1-1990 , (ieee standard test access port and boundary scan architecture). also referred to as jtag, this interface provides direct serial access to each of the transceivers i/o pins. this capability can be used during an in-circuit board test to increase the testability and reduce the cost of the in-circuit test process. the serial monitor output can be viewed as a real-time virtual probe for looking at the transceivers internal signals. the programmable signal source is shifted out serially at 16 times the symbol rate. most of the receive signal path is accessible through this output.
rs8973 1.0 system overview single-chip sdsl/hdsl transceiver 1.2 pin descriptions n8973dsd conexant 1-5 preliminary information 1.2 pin descriptions the rs8973 is packaged in a 100-pin plastic quad flat pack (pqfp). the pin assignments are shown in figure 1-3 . pin labels, numbers, and i/o assignments are listed in table 1-1 . figure 1-3. pin diagram 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 vdd1 cs rd /ds wr /r/w ale irq ready ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] dgnd dgnd vdd2 ad[7] motel muxed addr[7] addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] smon vdd1 rxbn rxbp rxn rxp agnd agnd txn agnd vaa txp nc nc nc nc atest2 atest1 vaa vaa agnd vtxn vtxp vccap vcomo vcomi rbias vaa vaa agnd vrxn vrxp dgnd dgnd vdd2 rst hclk xout dgnd vdd1 xtalo xtali/mclk vpll pgnd dtest1 dtest2 dtest3 vpll pgnd dtest4 agnd agnd 53 52 51 80 1 dgnd dgnd vdd2 tck tms tdi tdo dtest6 dtest5 tbclk rbclk rq[0]/bclk rq[1]/rdat qclk tq[0] tq[1]/tdat dgnd vdd1 agnd vaa rs8973 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 8973_004
1.0 system overview rs8973 1.2 pin descriptions single-chip sdsl/hdsl transceiver 1-6 conexant n8973dsd preliminary information table 1-1. pin descriptions pin pin label i/o pin pin label i/o pin pin label i/o pin pin label i/o 1 vdd1 C 26 addr[2] i 51 vrxp oa 76 agnd C 2cs i 27 addr[1] i 52 vrxn oa 77 rxp ia 3rd /ds i 28 addr[0] i 53 agnd C 78 rxn ia 4wr /r/w i 29 smon o 54 vaa C 79 rxbp ia 5 ale i 30 vdd1 C 55 vaa C 80 rxbn ia 6irq od 31 dgnd C 56 rbias oa 81 vaa C 7ready od 32 dgnd C 57 vcomi oa 82 agnd C 8 ad[0] i/o 33 vdd2 C 58 vcomo oa 83 vdd1 C 9 ad[1] i/o 34 rst i 59 vccap oa 84 dgnd C 10 ad[2] i/o 35 hclk o 60 vtxp oa 85 tq[1]/tdat i 11 ad[3] i/o 36 xout o 61 vtxn oa 86 tq[0] i 12 ad[4] i/o 37 dgnd C 62 agnd C 87 qclk o 13 ad[5] i/o 38 vdd1 C 63 vaa C 88 rq[1]/rdat o 14 ad[6] i/o 39 xtalo o 64 vaa C 89 rq[0]/bclk o 15 dgnd C 40 xtali/mclk i 65 atest1 ia 90 rbclk i 16 dgnd C 41 vpll C 66 atest2 ia 91 tbclk i 17 vdd2 C 42 pgnd C 67 nc oa 92 dtest5 i 18 ad[7] i/o 43 dtest1 i 68 nc oa 93 dtest6 i 19 motel i 44 dtest2 i 69 nc ia 94 tdo o 20 muxed i 45 dtest3 i 70 nc ia 95 tdi i 21 addr[7] i 46 vpll C 71 txp oa 96 tms i 22 addr[6] i 47 pgnd C 72 vaa C 97 tck i 23 addr[5] i 48 dtest4 i 73 agnd C 98 vdd2 C 24 addr[4] i 49 agnd C 74 txn oa 99 dgnd C 25 addr[3] i 50 agnd C 75 agnd C 100 dgnd C
rs8973 1.0 system overview single-chip sdsl/hdsl transceiver 1.2 pin descriptions n8973dsd conexant 1-7 preliminary information signal definitions are provided in table 1-2 . this is the coding used in the i/o column: o = digital output oa = analog output od = open-drain output i = digital input ia = analog input i/o = bidirectional nc = no connect table 1-2. hardware signal definitions (1 of 4) pin label signal name i/o definition microcomputer interface (mci) motel motorola/intel i selects between motorola and intel handshake conventions for the rd /ds and wr /r/w signals. motel = 1 for motorola protocol: ds , r/w motel = 0 for intel protocol: rd , wr ale address latch enable i falling-edge-sensitive input. the value of ad[7:0] when muxed = 1, or addr[7:0] when muxed = 0, is internally latched on the falling edge of ale. cs chip select i active-low input used to enable read/write operations on the mci. rd /ds read /data strobe i bimodal input for controlling read/write access on the mci. when motel = 1 and cs = 0, rd /ds behaves as an active-low data strobe ds . internal data is output on ad[7:0] when ds = 0 and r/w = 1. external data is internally latched from ad[7:0] on the rising edge of ds when r/w =0. when motel = 0 and cs = 0, rd /ds behaves as an active-low read strobe rd . internal data is output on ad[7:0] when rd = 0. write operations are not controlled by rd in this mode. wr / r/w write / read/write i bimodal input for controlling read/write access on the mci. when motel = 1 and cs = 0, wr /r/w behaves as a read/write select line r/w . internal data is output on ad[7:0] when ds = 0 and r/w = 1. external data is internally latched from ad[7:0] on the rising edge of ds when r/w =0. when motel = 0 and cs = 0, wr /r/w behaves as an active-low write strobe wr . external data is internally latched from ad[7:0] on the rising edge of wr . read operations are not controlled by wr in this mode. ad[7:0] address-data[7:0] i/o an 8-bit, bidirectional multiplexed address-data bus. ad[7] = msb, ad[0] = lsb. usage is controlled using muxed. addr[7:0] address bus (not multiplexed)[7:0] i provides a glueless interface to microcomputers with separate address and data buses. addr[7] = msb, addr[0] = lsb. usage is controlled using muxed. muxed addressing mode select i controls the mci addressing mode. when muxed = 1, the mci uses ad[7:0] as a multiplexed signal for address and data. when muxed = 0, the mci uses addr[7:0] as the address input, and ad[7:0] for data only. ready ready od active-low, open-drain output that indicates the mci is ready to transfer data. can be used to signal the microcomputer to insert wait states. irq interrupt request od active-low, open-drain output that indicates requests for interrupt. asserted whenever at least one unmasked interrupt flag is set. remains inactive whenever no unmasked interrupt flags are present.
1.0 system overview rs8973 1.2 pin descriptions single-chip sdsl/hdsl transceiver 1-8 conexant n8973dsd preliminary information rst reset i asynchronous, active-low, level-sensitive input that places the transceiver in an inactive state by setting the power-down mode bit of the global modes and status register [global_modes; 0x00], and zeroing the clk_freq [7:0] bits of the clock frequency select register [clock_freq;0x20], clk_freq[9,8] bits of the pll modes register [pll_modes; 0x22], and the hclk_freq[1,0] bits of the serial monitor source select register [serial_monitor_source; 0x01]. all ram contents are lost. does not affect the state of the test access port, which is reset automatically at power-up only. channel unit interface rq[1]/ rdat rq[0]/ bclk receive quat 1/ receive data receive quat 0/ bit clock o o rq[1]/rdat and rq[0]/bclk are bimodal outputs that represent the sign and magnitude bits of the received quaternary output symbol in parallel channel unit modes (rq[1], rq[0]), and the serial-data and bit-clock outputs in serial channel unit modes (rdat, bclk). behavior of these outputs is configurable through the channel unit interface modes register [cu_interface_modes; 0x06] for parallel master, parallel slave, serial magnitude-bit-first, and serial sign-bit-first operations. for parallel mode operation: rq[1] = sign bit output rq[0] = magnitude bit output both outputs are updated at the symbol rate on the rising edge of qclk (master mode) or the rising/falling edge (programmable) of rbclk (slave mode). for serial mode operation: rdat = serial quaternary data output bclk = bit-rate (two times symbol rate) clock output rdat is updated at the bit rate on the rising edge of bclk tq[1]/ tdat tq[0] transmit quat 1/ transmit data transmit quat 0 i i tq[1]/tdat and tq[0] are bimodal inputs that represent the sign and magnitude bits of the quaternary input symbol to be transmitted in parallel channel unit modes (tq[1], tq[0]), and the serial data input in serial channel unit modes (tdat). interpretation of these inputs is configurable through the channel unit interface modes register [cu_interface_modes; 0x06] for parallel master, parallel slave, serial magnitude-bit-first and serial sign-bit-first operations. for parallel mode operation: tq[1] = sign bit input tq[0] = magnitude bit input both inputs are sampled at the symbol rate on the falling edge of qclk (master mode) or the rising/falling edge (programmable) of tbclk (slave mode). for serial mode operation: tdat = serial quaternary data input tq0 = dont care (tie or pull up to supply rail) tdat is sampled at the bit rate (two times the symbol rate) on the falling edge of bclk. qclk quaternary clock o runs at the symbol rate. it defines the data on the tq and rq interfaces. qclk is also used to frame transmit/receive quats in serial mode. table 1-2. hardware signal definitions (2 of 4) pin label signal name i/o definition
rs8973 1.0 system overview single-chip sdsl/hdsl transceiver 1.2 pin descriptions n8973dsd conexant 1-9 preliminary information tbclk transmit baud-rate clock i functions as the transmit baud-rate clock input. it must be frequency-locked to qclk. this input is used only when the channel unit interface is in parallel slave mode. if it is unused, it should be tied to vdd2 or dgnd. rbclk receive baud-rate clock i functions as the receive baud-rate clock input. it must be frequency-locked to qclk. this input is used only when the channel unit interface is in parallel slave mode. if it is unused, it should be tied to vdd2 or dgnd. analog transmit interface txp, txn transmit positive, negative oa differential transmit line driver outputs. these signals are used to drive the subscriber line after passing through the hybrid and line transformer. analog receive interface rxp, rxn receive positive, negative ia differential receiver inputs. rxp and rxn receive the signal from the subscriber line. rxbp, rxbn receive balance positive, negative ia differential receiver balance inputs. rxbp and rxbn are used to subtract the echo of the signal being transmitted on the subscriber line. they should be connected to the txp, txn output pins through the hybrid circuit. this signal is subtracted from the signal being received by the rxp and rxn inputs in the vga. voltage reference generator interface rbias resistor bias oa connection point for external bias resistor. vcomo common mode voltage outputs oa common mode voltage for the analog circuitry. this pin should be connected to an external filtering capacitor. vcomi common mode voltage inputs oa common mode voltage for the analog circuitry. this pin should be connected to an external filtering capacitor. vccap voltage compensation capacitor oa analog voltage compensation capacitor. this pin should be connected to an external filtering capacitor. vrxp, vrxn receiver voltage reference positive, negative oa analog receive circuitry reference voltages. these pins should be connected to external filtering capacitors. vtxp, vtxn transmit voltage reference positive, negative oa analog transmit circuitry reference voltages. these pins should be connected to external filtering capacitors. clock interface xtali/ mclk crystal in/master clock i a bimodal input that can be used as the crystal input or as the master clock input. the frequency of the crystal or clock should be 10.24 mhz. xtalo crystal output o connection point for the crystal. if an external clock is connected to xtali/mclk, xtalo should be left floating. hclk high speed clock out o hclk can be configured to run at 16, 32, or 64 times the symbol rate. upon reset, it is set to 16 times the symbol rate. this clock will be phase locked to the incoming data when the rs8973 is configured as the remote unit. xout crystal clock out o buffered-crystal oscillator output. table 1-2. hardware signal definitions (3 of 4) pin label signal name i/o definition
1.0 system overview rs8973 1.2 pin descriptions single-chip sdsl/hdsl transceiver 1-10 conexant n8973dsd preliminary information test and diagnostic interface tdi jtag test data input i jtag test data input per ieee std 1149.1-1990. used for loading all serial instructions and data into internal test logic. sampled on the rising edge of tck. tdi can be left unconnected if it is not being used because it is pulled up internally. tms jtag test mode select i jtag test mode select input per ieee std 1149.1-1990. internally pulled-up input signal used to control the test-logic state machine. sampled on the rising edge of tck. tms can be left unconnected if it is not being used because it is pulled up internally. tdo jtag test data output o jtag test data output per ieee std 1149.1-1990. three-state output used for reading all serial configuration and test data from internal test logic. updated on the falling edge of tck. tck jtag test clock input i jtag test clock input per ieee std 1149.1-1990. used for all test interface and internal test logic operations. if unused, tck should be pulled low. smon serial monitor o serial data output used for real-time monitoring of internal signal-path registers. the source register is selected through the serial monitor source select register [serial_monitor_source; 0x01]. the 16-bit words are shifted out, lsb first, at 16 times the symbol rate. the rising edge of qclk defines the start lsb of each word. the output is updated on the rising edge of an internal clock running at 16 times qclk. dtest[1:4] digital tests 1C4 i active-high test inputs used by conexant to enable internal test modes. these inputs should be tied to digital ground (dgnd). dtest[5, 6] digital test 5, 6 i active-low test inputs used by conexant to enable internal test modes. these inputs should be tied to the i/o buffer power supply (vdd2). atest[1,2] analog test 1, 2 ia analog test inputs used by conexant for internal test modes. these inputs should be left floating (no connect, nc). power and ground vdd1 core logic power supply C dedicated supply pins powering the digital core logic functions. connect to 3.3 v. vdd2 i/o buffer power supply C dedicated supply pins powering the digital i/o buffers. connect to 5 v. vpll pll power supply C dedicated supply pins powering the pll and the crystal amplifier. connect to 5 v. pgnd pll ground C dedicated ground pins for the pll and the crystal amplifier. must be held at the same potential as dgnd and agnd. dgnd digital ground C dedicated ground pins for the digital circuitry. must be held at same potential as agnd and pgnd. vaa analog power supply C dedicated supply pins powering the analog circuitry. agnd analog ground C dedicated ground pins for the analog circuitry. must be held at the same potential as dgnd and pgnd. table 1-2. hardware signal definitions (4 of 4) pin label signal name i/o definition
rs8973 1.0 system overview single-chip sdsl/hdsl transceiver 1.3 regenerator configuration n8973dsd conexant 1-11 preliminary information 1.3 regenerator configuration figure 1-4 shows the interconnection between two rs8973s for a single loop regenerator system. bt8953a/rs8953b provides an internal cross-connect data path between reg-r and reg-c. hclk on regCr is configured to run at 16 times the symbol rate, which is the power-on default. the reg_clk_en bit of miscellaneous/test register (0x0f) is reset (0) on regCr. the reg_clk_en bit of miscellaneous/test register (0x0f) is set (1) on regCc. in this mode, the internal clock synthesizer is bypassed. figure 1-4. regenerator system block diagram 10.24 mhz regCr to cot bt8953a/ rs8953b xtali/mclk (40) xtalo (39) rs8973 hclk (35) to rt regCc xtali/mclk (40) xtalo (39) rs8973 hclk (35) nc 8973_005
1.0 system overview rs8973 1.3 regenerator configuration single-chip sdsl/hdsl transceiver 1-12 conexant n8973dsd preliminary information
n8973dsd conexant 2-1 preliminary information 2 2.0 functional description 2.1 transmit section the transmit section block diagram is shown in figure 2-1 . it comprises five major functions: a symbol source selector/scrambler, a variable gain digital-to-analog converter (dac), a pulse-shaping filter, an analog ct reconstruction filter, and a line driver. figure 2-1. transmit section block diagram transmit channel unit interface symbol source/ scrambler variable-gain dac line driver control registers tq[1,0] txp txn isolated pulses detector loopback ones (1s) pulse- shaping filter analog ct reconstruction filter 8973_006
2.0 functional description rs8973 2.1 transmit section single-chip sdsl/hdsl transceiver 2-2 conexant n8973dsd preliminary information 2.1.1 symbol source selector/scrambler the input source selector/scrambler can be configured through the transmitter modes register [transmitter_modes; 0x0b] data_source [2:0] bits. it selects the source of the data to be transmitted and determines whether the data is scrambled. the symbol source selector/scrambler modes are described in table 2-1 . the bit stream is converted into symbols for the four-level cases, as shown in table 2-2 . table 2-1. symbol source selector/scrambler modes data_source[2:0] symbol source selector/scrambler mode 000 isolated pulse. level selected by isolated_pulse[1,0]. the meter timer must be enabled and in continuous mode. the pulse repetition interval is determined by the meter timer countdown interval. 001 four-level scrambled detector loopback. sign and magnitude bits from the receiver detector are scrambled and looped back to the transmitter. feedback polynomial determined by the htur_lfsr control bit. 010 four-level unscrambled data. transmits the four-level (2b1q) sign and magnitude bits from the transmit channel unit transmit interface without scrambling. 011 four-level scrambled 1s. transmits a scrambled, constant high-logic level as a four-level (2b1q) signal. feedback polynomial determined by the htur_lfsr control bit. 100 alternating symbol mode. outputs symbols of alternating polarity. level is selected by isolated_pulse [1:0]. the meter timer must be enabled and in continuous mode. the half period of the output signal is defined by the meter timer countdown interval. 101 four-level scrambled data. scrambles and transmits the four-level (2b1q) sign and magnitude bits from the channel unit transmit interface. feedback polynomial determined by the htur_lfsr control bit. 110 two-level unscrambled data. constantly forces the magnitude bit from the transmit channel unit interface to a logic 0, and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. valid output levels are limited to + 3 and C 3. 111 two-level scrambled 1s. transmits a scrambled, constant high-logic level as a two-level signal. feedback polynomial determined by the htur_lfsr control bit. scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal, while the magnitude bit is sourced with a constant logic 0. valid output levels are limited to + 3 and C 3. table 2-2. four-level bit-to-symbol conversions first input bit (sign) second input bit (magnitude) output symbol 00C 3 01C 1 11+ 1 10+ 3
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.1 transmit section n8973dsd conexant 2-3 preliminary information in two-level mode, the magnitude bit is forced to a 0. this forces the symbols to be + 3 and C 3, as shown in table 2-3 . the scrambler is essentially a 23-bit-long linear feedback shift register (lfsr). the feedback points are programmable for central office and remote terminal applications using the htur_lfsr bit of the transmitter modes register. the lfsr polynomials for local (htu-c/ltu) and remote (htu-r/ntu) unit operations are: the scrambler operates differently depending on whether a two-level or four-level mode is specified. in two-level scrambled-1s mode, the lfsr is clocked once per symbol; in four-level mode, the lfsr is clocked twice per symbol. the transmitter modes register can also be used to zero the output of the transmitter using the transmitter_off control bit. the rs8973 can generate isolated pulses to support the testing of pulse templates. when in the isolated pulse mode, the output consists of a single pulse surrounded by 0s. note: zero is not a valid 2b1q level and occurs only in this special mode or when the transmitter is off. the repetition rate of the pulses is controlled by the meter timer. any of the four 2b1q levels can be chosen through the transmitter modes registers isolated_pulse[1,0] control bits. 2.1.2 variable gain digital-to-analog converter a four-level dac is integrated into the rs8973 to convert the output of the symbol source to analog form. the normalized values of these four analog levels are + 3, + 1, C 1 and C 3. each represents a symbol, or quat. to provide precise adjustment of transmitted power, the level of the dac can be adjusted. the transmitter gain register [tx_gain; 0x29] sets the level. during the manufacturing of the rs8973, process variations can cause changes in transmitter levels. the transmitter calibration register [tx_calibrate; 0x28] contains a read-only value which nulls this variation. the value in this register is determined for each rs8973 device during production testing. upon initialization, the transmitter gain register should be loaded based on the transmitter calibration register. if there are other sources of transmit power variation (e.g., a nonstandard hybrid or attenuative lightening protection), the transmitter gain must be adjusted to include these effects. the range of adjustment of the transmitter gain is from C 1.60 db to 1.40 db. table 2-3. two-level bit-to-symbol conversions first input bit (sign) second input bit (magnitude) output symbol 0 dont care C 3 1 dont care + 3 local x 23 C x 5 C 1 ?? t remote x 23 C x 18 C 1 ?? t
2.0 functional description rs8973 2.1 transmit section single-chip sdsl/hdsl transceiver 2-4 conexant n8973dsd preliminary information 2.1.3 pulse-shaping filter the pulse-shaping filter is used to filter the quats output from the variable-gain dac. this filter, when combined with other filtering in the signal path, produces a transmitted signal on the line that meets the power spectral density, the transmitted power, and the pulse-shaping requirements, as specified in chapter 5.0, electrical and mechanical specifications . 2.1.4 analog ct reconstruction filter the analog ct reconstruction filter removes the discrete-time images from the transmit signal before it is amplified by the line driver. 2.1.5 line driver the line driver buffers the output of the ct reconstruction filter to drive diverse loads. the output of the line driver is differential.
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.2 receive section n8973dsd conexant 2-5 preliminary information 2.2 receive section like the transmit section, the receive section consists of both analog and digital circuitry. the vga provides the interface to the analog signals received from the line and the hybrid. the adc then digitizes the analog signal so it can be further processed in the dsp section of the receiver. the receiver dsp section includes front-end processing, echo cancellation, equalization, and symbol detection. 2.2.1 variable gain amplifier the vga has two purposes. the first is to provide a dual-differential analog input so the pseudo-transmit signal created by the hybrid can be subtracted from the signal received from the line transformer. this subtraction provides first-order echo cancellation, which results in a first-order approximation of the signal received from the line. figure 2-2 illustrates the recommended echo-cancellation circuit interconnections. all off-chip circuitry, including the hybrid and anti-alias filters, consists entirely of passive components. further echo cancellation occurs in the receiver dsp. the second purpose of the vga is to provide programmable gain of the received signal prior to passing it to the adc. this reduces the resolution required for the adc. there are six gain settings ranging from 0 db to 15 db (this is the gain setting range in relative terms; the physical settings range from C 3 db to 12 db). the gain is controlled through the gain[2:0] control bits in the adc control register [adc_control; 0x21]. see chapter 3.0, registers , for a more detailed description of the gain[2:0] control bits. 2.2.2 analog-to-digital converter the adc provides 16 bits of resolution. the analog input from the variable gain amplifier is converted into digital data and output at the symbol rate. figure 2-2. first-order echo cancellation using the variable gain amplifier rxp rxn rxbp rxbn txp txn line (twisted pair) to adc on-chip circuitry off-chip circuitry line impedance matching resistors gain[2:0] hybrid anti-alias filter anti-alias filter + C + C + C + C + C + C line driver line transformer 8973_007
2.0 functional description rs8973 2.2 receive section single-chip sdsl/hdsl transceiver 2-6 conexant n8973dsd preliminary information 2.2.3 digital signal processor the dsp includes five least mean squared (lms) filters: ? echo canceller (ec) ? digital automatic gain controller (dagc) ? feed forward equalizer (ffe) ? error predictor (ep) ? decision feedback equalizer (dfe). these filters are used to equalize the received signal so that the symbols transmitted from the far-end can be reliably recovered. the dsp uses symbol rate sampling for all processing functions. figure 2-3 shows the interconnections and relationships to the digital front-end and the detector. figure 2-3. receiver digital signal processing digital front-end channel unit interface echo canceller transmit symbol equalizer dfe detector lec slm ffe dagc nec ep pkd slicer felm is filter 8973_008 CC CC C C
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.2 receive section n8973dsd conexant 2-7 preliminary information 2.2.3.1 digital front-end prior to the main signal processing, the input signal must be adjusted for any dc offset. the front-end module also monitors the input signal level, which includes measuring dc and ac input signal levels, detecting and counting overflows, and detecting alarms based on the far-end signal level. figure 2-4 summarizes the features of the digital front-end module. figure 2-4. digital front-end block diagram echo-free signal from nec dc offset from mci accumulator result register far-end level meter comparator comparator far-end alarms high threshold from mci low threshold from mci high_felm interrupt low_felm interrupt result register accumulator dc level meter accumulator absolute value result register signal level meter adc data r, to ec + C overflow detector counter result register overflow monitor overflow absolute value 8973_009
2.0 functional description rs8973 2.2 receive section single-chip sdsl/hdsl transceiver 2-8 conexant n8973dsd preliminary information 2.2.3.2 offset adjustment a nonzero dc level on the input can be corrected by a dc offset value [dc_offset_low, dc_offset_high; 0x26, 0x27], which is subtracted from the input. the dc offset is a 16-bit number and is programmed through the microcomputer interface. 2.2.3.3 dc level meter the dc level meter provides the monitoring needed for adaptive offset compensation. the offset-adjusted input signal is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. the 16 msbs are placed into the dc level meter registers [dc_meter_low, dc_meter_high; 0x44, 0x45]. 2.2.3.4 signal level meter the signal level meter provides the monitoring needed for adjusting the analog gain circuit located before the adc. the absolute value of the offset adjusted input signal is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. the 16 msbs are placed in the signal level meter registers [slm_low, slm_high; 1; 0x46, 0x47]. 2.2.3.5 overflow detection and monitoring the overflow sensor detects adc overflows. the overflow monitor counts the number of overflows, as indicated by the overflow sensor during the meter timer interval [meter_low, meter_high; 0x18, 0x19]. the counter is limited to 8 bits. in the case of 256 or more overflows during the measurement interval, the counter will hold at 255. the counter is loaded into the overflow meter register [overflow_meter; 0x42] at the end of each measurement interval. 2.2.3.6 far-end level meter the far-end level meter monitors the output of the echo canceller, which is called the far-end signal because the echo of the transmitted signal is subtracted from it. this value is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. the 16 msbs are placed into the far-end level meter register [felm_low, felm_high; 0x48, 0x49]. 2.2.3.7 far-end level alarm the result of the far-end level meter is compared to two thresholds. when these are exceeded, an interrupt is sent to the microcomputer interface if the corresponding felm interrupt is enabled. the thresholds are determined by the value in the far-end high alarm threshold registers [far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30, 0x31] and the far-end low alarm threshold registers [far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x32, 0x33]. the interrupts high_felm and low_felm are bits 2 and 1, respectively, of the irq source register [irq_source; 0x05]. the interrupts high_felm and low_felm can be masked by writing a 1 to bits 2 and 1, respectively, of the interrupt mask register high [mask_high_reg; 0x03]. 2.2.4 impulse shortening filter the impulse shortening (is) filter is a high pass filter which pre-equalizes the channel and eliminates long tails caused by the transformer.
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.2 receive section n8973dsd conexant 2-9 preliminary information 2.2.5 echo canceller the echo canceller (ec) removes images of the transmitted symbols from the received signal and consists of two blocks: a linear and nonlinear echo canceller. the organization of the blocks is displayed in figure 2-3, receiver digital signal processing . 2.2.5.1 linear echo canceller the linear echo canceller (lec) is a conventional lms, finite impulse response (fir) filter, which removes linear images of the transmitted symbols from the received signal. it consists of a 120-tap fir filter with 32-bit adapted coefficients. when lec is enabled, the last data tap of the echo canceller is treated specially; the data value is set to a constant 1. this serves to cancel any dc offset that may be present. these modes, used less often, can also be enabled through the mci: ? a freeze coefficient mode disables the coefficient updates. ? a special mode zeros all of the coefficients. ? an additional mode zeros the output of the fir with no effect on the coefficients. ? individual ec coefficients can be read and written through the mci. 2.2.5.2 nonlinear echo canceller (nec) the nonlinear echo canceller (nec) reduces the residual echo power in the echo canceller output caused by nonlinear effects in the transmitter, receiver, analog hybrid circuitry, or line cables. the delay of the transmit-symbol input to the nec can be specified through the mci, nonlinear echo canceller mode register [nonlinear_ec_modes; 0x09]. this allows the nec to operate on the peak of the echo regardless of differing delays in the echo path. these modes, used less often, can also be enabled through the mci: ? a freeze coefficient mode disables the coefficient updates. ? a special mode zeros all of the coefficients. ? an additional mode zeros the output of the look-up table with no effect on the coefficients. ? the 64 14-bit, individual nec coefficients can be read and written through the mci. 2.2.6 equalizer four lms filters are used in the equalizer to process the echo canceller output so that received symbols can be reliably recovered. the filters are a digital automatic gain controller, a feed forward equalizer, an error predictor, and a decision feedback equalizer. their interconnections are shown in figure 2-3, receiver digital signal processing . 2.2.6.1 digital automatic gain control the digital automatic gain control (dagc) scales the echo-free signal to the optimum magnitude for subsequent processing. two other modes, used less often, can also be enabled through the mci: ? a freeze coefficient mode disables the coefficient update. ? the dagc gain coefficient can be read or written through the mci.
2.0 functional description rs8973 2.2 receive section single-chip sdsl/hdsl transceiver 2-10 conexant n8973dsd preliminary information 2.2.6.2 feed forward equalizer the feed forward equalizer (ffe) removes precursors from the received signal. the ffe can be operated in a special adapt last mode. in this mode, which is useful during startup, only the last coefficient is updated. the last coefficient is multiplied with the oldest data sample (sample #7). other modes, used less often, can be enabled through the mci: ? a freeze coefficient mode disables the coefficient updates. ? a special mode zeros all of the coefficients. ? individual ffe coefficients can be read and written through the mci. 2.2.6.3 error predictor the error predictor (ep) improves the performance of the equalizer by prognosticating errors before they occur. other modes, used less often, can be enabled through the mci: ? a freeze coefficient mode disables the coefficient updates. ? a special mode zeros all of the coefficients. ? individual ep coefficients can be read and written through the mci. 2.2.6.4 decision feedback equalizer the decision feedback equalizer (dfe) removes postcursors from the received signal. other modes, used less often, can be enabled through the mci: ? a freeze coefficient mode disables the coefficient updates. ? a zero coefficients mode zeros all of the coefficients. ? a zero filter output mode zeros the output of the fir with no effect on the coefficients. ? individual dfe coefficients can be read and written through the mci. 2.2.6.5 microcoding the dagc, ffe, and ep filters are implemented using an internal microprogrammable dsp, optimized for lms filters. internal dsp micro-instructions are stored in an on-chip ram. this microcode ram is loaded after power-up through the mci when the transceiver is initialized. 2.2.7 detector the detector converts the equalized received signal into a 2b1q symbol and produces two error signals used in adapting the receiver equalizers. the signal detection uses two sub-blocks, a slicer, and a peak detector. additionally, the detector contains a scrambler and bit error rate (ber) meter for use during the start-up sequence. 2.2.7.1 slicer the slicer thresholds the equalized signal to produce a 2b1q symbol. the input to the slicer is the ffe output minus the dfe and ep outputs. the slicer can operate in two modes: two-level and four-level. in the two-level mode, which is used during start-up when the only transmitted symbols are + 3 or C 3, the slicer threshold is set at zero. in the four-level mode, the cursor level is specified through the mci. it is a 16-bit, 2s complement number, but must be positive and less than 0x2aaa for proper operation. 2.2.7.2 peak detector the peak detector (pkd) is used only during the two-level transmission part of start-up. it operates on the echo-free signal. a signal is detected to be a + 3 if it is higher than both of its neighbors, or a C 3 if it is lower than both of its neighbors. if neither of the peaked conditions exist, the output of the slicer is used. 2.2.7.3 error signals the detector computes two error signals for use in the equalizer: a 16-bit slicer and a 16-bit equalizer.
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.2 receive section n8973dsd conexant 2-11 preliminary information 2.2.7.4 scrambler module the scrambler can operate as either a scrambler or as a descrambler. the scrambler block is used during the scrambled-1s part of the start-up sequence. this provides an error-free signal for equalizer adaptation. this scrambler is essentially a 23-bit-long linear feedback shift register (lfsr). the feedback point depends on whether the transceiver is being used in a central-office or remote-terminal application. when the lfsr is operating as a descrambler, the input source is the detector output. the symbol is converted to a bit stream as shown in table 2-4 for the two-level case. the symbol is converted to a bit stream as shown in table 2-5 for the four-level case. the lfsr operates in the same way in both cases, except that in the two-level case it is clocked once per symbol, and in the four-level case it is clocked twice per symbol. when operating as a scrambler, the lfsr must first be locked to the far-end source. once locked, it is then able to replicate the far-end input sequence when its input is held at all 1s. the locking sequence is controlled internally, initiated through the mci by setting the lfsr_lock bit of the detector_modes register. the locking sequence consists of the following four steps: 1. operate the lfsr as a descrambler for 23 bits. 2. operate the lfsr as a scrambler for 127 bits. the sync detector is active during this period. 3. go to step 1 if synchronization was not achieved; otherwise, continue to step 4. 4. send an interrupt to the microcomputer if unmasked, indicating successful locking, and continue operating as a scrambler. the sequence continues until the lfsr_lock control bit is cleared by the microcomputer. table 2-4. two-level symbol-to-bit conversion input symbol output bit C 3 0 + 3 1 table 2-5. four-level symbol-to-bit conversion input symbol first output bit (sign) second output bit (magnitude) C 3 0 0 C 1 0 1 + 1 1 1 + 3 1 0
2.0 functional description rs8973 2.2 receive section single-chip sdsl/hdsl transceiver 2-12 conexant n8973dsd preliminary information 2.2.7.5 sync detector the sync detector compares the output of the scrambler with the output of the symbol detector. the number of equivalent bits is accumulated for 128 comparisons. the result is then compared to a scrambler synchronization threshold register [scr_sync_th; 0x2e], a lock is declared, and the sync bit of the irq_source register is set if the count is greater than the threshold. for a count less than or equal to the threshold, no lock condition is declared and the sync bit is unaffected. 2.2.7.6 detector meters the detector consists of five meters: a ber meter, a symbol histogrammer, a noise-level meter, a noise-level histogram meter, and an snr alarm meter. ber meter the ber meter provides an estimate of the bit error rate when the received symbols are known to be scrambled 1s. when the lfsr is operating as a descrambler, the meter counts the number of 1s on the descrambler output. when the lfsr is operating as a scrambler, the ber meter counts the number of equal scrambler and symbol detector outputs. the counter operates over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. the counter is saturated to 16 bits. at the end of the measurement interval the counter is loaded into the bit error rate meter registers [ber_meter_low, ber_meter_high; 0x4c, 0x4d]. symbol histogrammer the symbol histogrammer computes a coarse histogram of the received symbols. it operates by counting the number of 1s received during the meter timer interval [meter_low, meter_high; 0x18, 0x19]. that is, at the start of the measurement interval a counter is cleared. for each detector output which is + 1 or C 1, the counter is incremented. if the detector output is + 3 or C 3, the count is held at its previous value. the count is saturated to 16 bits. at the end of the measurement interval, the 8 msbs of the counter are loaded into the symbol histogram meter register [symbol_histogram; 0x4e]. this can be used during start-up to detect the transition from two-level to four-level signalling. noise level meter the noise level meter estimates the noise at the input to the slicer. it operates by accumulating the absolute value of the slicer error over meter timer interval [meter_low, meter_high; 0x18, 0x19]. at the end of the measurement interval, the 16 msbs of the 32-bit accumulator are loaded into the noise level meter register [nlm_low, nlm_high; 0x50, 0x51]. noise level histogram meter the noise level histogram meter counts the number of high noise-level conditions which occur during each meter countdown interval. a high noise-level condition is defined as the absolute value of the slicer error signal exceeding the threshold specified in the noise level histogram threshold register [0x2a,2b]. snr alarm the snr alarm provides a rapid indication of impulse noise disturbances and loss of signal so that corrective action can be taken. the alarm is based on a second noise level meter. the meter is the same as the preceding noise level meter except it operates on a dedicated timer, the snr alarm timer. the absolute value of the slicer error is accumulated during the timer period. at the end of the measurement interval, the 16 msbs of the accumulator are compared against the snr alarm threshold register [snr_alarm_th_low, snr_alarm_th_high; 0x34, 0x35]. if the result is greater than this threshold, an interrupt is set in the irq_source register. the threshold is set through the mci.
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.3 timing recovery and clock interface n8973dsd conexant 2-13 preliminary information 2.3 timing recovery and clock interface the timing recovery and clock interface block consists of the timing recovery circuit, the crystal amplifier, and the clock synthesizer, as detailed in figure 2-5 . the main purpose of this circuitry is to generate the internal clocks, including bclk and qclk, from the 10.24 mhz input mclk, based on the selected data rate, and to recover the clock from received data. control fields include the following: ? clock frequency select register [clk_select; 0x20] ? pll modes register [clk_select; 0x22] ? hclk_freq[1,0] bits of the serial monitor source select register [serial_monitor_source; 0x01] ? pll modes register [pll_modes; 0x22] ? timing recovery pll phase offset register [pll_phase_offsset_low, pll_phase_offset_high; 0x24, 0x25] ? pll frequency register [pll_frequency_low, pll_frequency_high; 0x5e, 0x5f]. see chapter 3.0, registers , for descriptions of these control fields.
2.0 functional description rs8973 2.3 timing recovery and clock interface single-chip sdsl/hdsl transceiver 2-14 conexant n8973dsd preliminary information figure 2-5. timing recovery and clock interface block diagram 8973_010 hclk (35) qclk (87) xout (36) xtali (40) c10 c11 y1 = 10.24 mhz (for all data rates) y1 timing recovery circuit detected symbol equalizer error crystal amplifier control registers phase detector meter register [0x40, 0x41] clock synthesizer xtalo (39)
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.3 timing recovery and clock interface n8973dsd conexant 2-15 preliminary information 2.3.1 timing recovery circuit the timing recovery circuit uses the rs8973s internal detected symbol and equalizer error signals to regenerate the received data symbol clock (qclk). the hclk output is synchronized with the edges of the symbol clock (qclk), unlike the xout output, which is a buffered output of the crystal amplifier. hclk can be programmed for rates of 16, 32, or 64 times the symbol rate. the timing recovery circuit includes a phase detector meter that measures the average value of a phase correction signal. this information can be used during start-up to set the phase offset in the receive phase select register [receive_phase_select; 0x07]. the output of the phase detector is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. at the end of the measurement interval, the value is loaded into the phase detector meter register [pdm_low, pdm_high; 0x40, 0x41]. the user can also bypass the timing recovery circuit and directly specify the frequency through the pll frequency register [pll_frequency_low, pll_frequency_high; 0x5e, 0x5f]. 2.3.2 crystal amplifier the crystal amplifier reduces the support circuitry needed for the rs8973 by eliminating the need for an external crystal oscillator (xo). a crystal of 10.24 mhz frequency can be connected directly to the xtali and xtalo pins. the crystal amplifier can also accommodate an external clock input by connecting the external clock to the xtali input pin. 2.3.3 clock synthesizer the clock synthesizer takes the 10.24 mhz input clock as a reference and generates internal clocks required for data rates ranging from 144 kbps to 2320 kbps. the appropriate internal clock frequency can be selected by specifying the data rate in the clock frequency select register [clk_select [7:0]; 0x20] and pll modes register [clk_select [9,8]; 0x22].
2.0 functional description rs8973 2.4 channel unit interface single-chip sdsl/hdsl transceiver 2-16 conexant n8973dsd preliminary information 2.4 channel unit interface the quaternary signals of the channel unit interface have four modes which are programmable through bits 0 and 1 of the channel unit interface modes register [cu_interface_modes; 0x06]. they are serial sign-bit first, serial magnitude-bit first, parallel master, and parallel slave. in serial mode, a bit-rate clock (bclk) is output at twice the symbol rate. the sign and magnitude bits of the receive data are output through rdat on the rising edge of bclk. the sign and magnitude bits of the transmit data are sampled on the falling edge of bclk at the tdat input. the sign bit is transferred first, followed by the magnitude bit of a given symbol in sign-bit first mode, while the opposite occurs in magnitude-bit first mode. the clock relationships for serial sign-bit first mode are illustrated in figure 2-6 . in parallel master mode, the sign and magnitude receive data is output through rq[1] and rq[0], respectively, on the rising edge of qclk. the quaternary transmit data is sampled on the falling edge of qclk. this clock and data relationship is illustrated in figure 2-7 . figure 2-6. serial sign-bit first mode figure 2-7. parallel master mode qclk bclk rdat tdat sign 0 magnitude 0 bit-rate clock sign 1 magnitude 1 sign 2 sign 0 magnitude 0 sign 1 magnitude 1 sign 2 8973_011 qclk sign 0 sign 2 sign 1 magnitude 0 magnitude 1 magnitude 2 rq[1]/tq[1] 8973_012 rq[0]/tq[0]
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.4 channel unit interface n8973dsd conexant 2-17 preliminary information the parallel slave mode uses rbclk and tbclk inputs to synchronize data transfer. rbclk and tbclk must be frequency-locked to qclk, though the use of two internal fifos allows an arbitrary phase relationship to qclk. tq[1] and tq[0] are sampled on the active edge of tbclk, as programmed through the mci. rq[1] and rq[0] are output on the active edge of rbclk, also as programmed through the mci. figure 2-8 shows the clock relationships, when tbclk is programmed to be falling-edge active and rbclk is rising-edge active. figure 2-8. parallel slave mode tbclk sign 0 sign 2 sign 1 magnitude 0 magnitude 1 magnitude 2 tq[1] tq[0] rbclk sign 0 sign 2 sign 1 magnitude 0 magnitude 1 magnitude 2 rq[1] rq[0] 8973_013
2.0 functional description rs8973 2.5 microcomputer interface single-chip sdsl/hdsl transceiver 2-18 conexant n8973dsd preliminary information 2.5 microcomputer interface the microcomputer interface provides operational mode control and status through internal registers. a microcomputer write sets the operating modes to the appropriate registers. a read to a register verifies the operating mode or provides the status. the mci can be programmed to generate an interrupt on certain conditions. 2.5.1 source code conexant provides portable c-source code under a no-cost licensing agreement. this source code provides a start-up procedure, as well as diagnostic and system monitoring functions. 2.5.2 microcomputer read/write the mci uses either an 8-bit-wide multiplexed address-data bus, or an 8-bit-wide data bus and a separate 8-bit-wide address bus for external data communications. the interface provides access to the internal control and status registers, coefficients, and microcode ram. the interface is compatible with intel or motorola microcomputers, and is configured with the inputs, motel and muxed. ?motel high selects motorola-type microcomputer and uses control signals ale, cs , ds , and r/w . motel low selects intel-type microcomputer and uses control signals ale, cs , rd , and wr . ? muxed high configures the interface to use the multiplexed address-data bus with both the address and data on the ad[7:0] pins. muxed low configures the interface to use separate address and data bus with the data on the ad[7:0] pins and the address on the addr[7:0] pins. ? the ready pin is provided to indicate when the rs8973 is ready to transfer data and can be used by the microcomputer to insert wait states in read or write cycles. the mci provides access to a 256-byte internal address space. the registers in this address space provide configuration, control, status, and monitoring capabilities. meter values are read lower-byte, then upper-byte. when the lower-byte is read, the upper-byte is latched at the corresponding value. this ensures that multiple byte values correspond to the same reading. most information can be directly read or written; however, the filter coefficients require an indirect access.
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.5 microcomputer interface n8973dsd conexant 2-19 preliminary information 2.5.2.1 ram access registers the internal ram of the scratch pad, lec, nec, dfe, equalizer, and microcode are accessed indirectly. they all share a common data register which is used for both read and write operations: access data register [access_data_byte[3:0]; [0x7cC0x7f]. each ram has an individual read select and write select register. writes to these registers specify the location to access and trigger the actual ram read or write. to perform a read, the address of the desired ram location is first written to the corresponding read tap select register. two symbol periods afterward, the individual bytes of that location are available for reading from the access data register. to perform a write, the value to be written is first stored in the access data register. the address of the affected ram location is then written to the corresponding write tap select register. when writing the same value to multiple locations, it is not necessary to rewrite the access data register. to ensure reliable access to the embedded ram, internal read and write operations are performed synchronous to the symbol clock. this limits access to the internal ram to one every other cycle. when reading or writing multiple filter coefficients, it may be desirable to freeze adaptation so that all values correspond to the same state. 2.5.2.2 multiplexed address/data bus the timing for a read or write cycle is stated explicitly in chapter 5.0, electrical and mechanical specifications . during a read operation, an external microcomputer places an address on the address-data bus, which is then latched on the falling edge of ale. data are placed on the address-data bus after cs and rd, or cs and ds go low. the read cycle is completed with the rising edge of cs or rd or ds . a write operation latches the address from the address-data bus at the falling edge of ale. the microcomputer places data on the address-data bus after cs , and wr or cs and ds go low. motorola mci has r/w falling edge preceding the falling edge of cs and ds . the rising edge of r/w occurs after the rising edge of cs and ds . data are latched from the address-data bus on the rising edge of cs or wr or ds . 2.5.2.3 separated address/ data bus the timing for a read or write cycle using the separated address and data buses is essentially the same as over the multiplexed bus. the one exception is that the address must be driven onto the addr[7:0] bus rather than the ad[7:0] bus. 2.5.3 interrupt request the 12 interrupt sources consist of 8 timers, a far-end signal high alarm, a far-end signal low alarm, a snr alarm, and a scrambler synchronization detector. all of the interrupts are requested on a common pin, irq . each interrupt can be individually enabled or disabled through the interrupt mask registers [mask_low_reg, mask_high_reg; 0x02, 0x03]. the cause of an interrupt is determined by reading the timer source register [timer_source; 0x04] and the irq source register [irq_source; 0x05]. the timer interrupt status is set only when the timer transitions to zero. alarm interrupts cannot be cleared while the alarm is active. in other words, it cannot be cleared while the condition still exists. irq is an open-drain output and must be tied to a pull-up resistor. this allows irq to be tied to a common interrupt request.
2.0 functional description rs8973 2.5 microcomputer interface single-chip sdsl/hdsl transceiver 2-20 conexant n8973dsd preliminary information 2.5.4 reset the reset input (rst ) is an active-low input that places the transceiver in an inactive state by setting the mode bit (0) in the global modes and status register [global_modes; 0x00]. an internal supply monitor circuit ensures that the transceiver is in an inactive state upon initial application of power to the chip. 2.5.5 registers the rs8973 has many directly addressable registers that include control and monitoring functions. write operations to undefined registers have unpredictable effects. read operations from undefined registers have undefined results. 2.5.6 timers eight timers are integrated into the rs8973 to control the various on-chip meters and to aid the microcomputer in stepping through the events of the start-up sequence. the structure of each timer includes down counter, zero detect logic, and control circuitry, which determines when the counter is reloaded or decremented. for each of the 8 timers, there is a 2-byte timer interval register that determines the value from which the timer decrements. there are three 8-bit registers: ? timer restart register [timer_restart; 0x0c] ? timer enable register [timer_enable; 0x0d] ? timer continuous mode register [timer_continuous; 0x0e]. these registers control the operation of the timers. each bit of the 8-bit registers corresponds to a timer. each logic-high bit in timer_restart acts as an event that causes the corresponding timer to reload. each logic-high bit in timer_enable acts to enable the corresponding timer. each logic-high bit in timer_continuous acts to reload the counter after timing out. each counter is loaded with the value in its interval register. the counter decrements until it reaches zero. upon reaching zero, an interrupt is generated if enabled by the interrupt mask low register [mask_low_reg, mask_high_reg; 0x02, 0x03]. the interrupt is edge-triggered so that only one interrupt is caused by a single time-out. a prescaler can precede the timer. this increases the time span available at the expense of resolution. only the start-up timers have prescalers. table 2-6 provides summary information on the timers.
rs8973 2.0 functional description single-chip sdsl/hdsl transceiver 2.5 microcomputer interface n8973dsd conexant 2-21 preliminary information four timers are provided for use in timing start-up events. these timers share a single prescaler, which divides the symbol clock by 1024 and supplies this slow clock to the four counters. the timers are startup timer 1, startup timer 2, startup timer 3, and startup timer 4. each one is independent, with separate interval timer values and interrupts. two timers control the measurement intervals for the various meters: the snr alarm timer and the meter timer. the snr alarm timer is used only by the low snr, while the meter timer is used by all other meters, excluding the low snr meter. their respective interrupts are set when each of these two timers expires. there are no prescalers for these timers; they count at the symbol rate. both timers are normally used in the continuous mode. two identical timers are provided for general use: general purpose timer 3 and general purpose timer 4. there are no prescalers for these timers; they count at the symbol rate. each timer signals an interrupt when it expires. 2.5.7 scratch pad memory the scratch pad memory consists of 64 bytes of ram available to the external microcomputer. this is used by conexant-supplied software to minimize system memory requirements. table 2-6. timers timer name purpose clock rate control bits startup timer 1 startup events symbol rate ? 1024 sut 1 startup timer 2 startup events symbol rate ? 1024 sut 2 startup timer 3 startup events symbol rate ? 1024 sut 3 startup timer 4 startup events symbol rate ? 1024 sut 4 snr alarm timer snr measurement symbol rate snr meter timer measurement symbol rate meter general purpose timer 3 miscellaneous symbol rate t3 general purpose timer 4 miscellaneous symbol rate t4
2.0 functional description rs8973 2.6 test and diagnostic interface (jtag) single-chip sdsl/hdsl transceiver 2-22 conexant n8973dsd preliminary information 2.6 test and diagnostic interface (jtag) to access individual chips for pcb verification, special circuitry is incorporated within the transceiver, which complies with ieee std 1149.1-1990, standard test access port and boundary scan architecture set by the joint test action group (jtag). jtag has four dedicated pins that comprise the test access port (tap): 1. test mode select (tms) 2. test clock (tck) 3. test data input (tdi) 4. test data out (tdo) verification of the integrated circuits connection to other modules on the printed circuit board can be achieved through these four tap pins. jtags approach to testability uses boundary scan cells placed at each digital pin, both inputs and outputs. all scan cells are interconnected in a boundary-scan register which applies or captures test data used for functional verification of the pc board interconnection. jtag is particularly useful for board testers using functional testing methods. the boundary-scan cells at each digital pin provide the ability to apply and capture the respective logic levels. since all of the digital pins are interconnected as a long shift register, the tap logic has access and control of all necessary pins to verify connectivity. for mixed signal ics, the chip boundary definition is expanded to include the on-chip interface between digital and analog circuitry. during a power-up sequence, internal supply-monitor circuitry ensures that each pin is initialized to operate as a 2b1q transceiver, instead of jtag test mode. the jtag standard defines an optional device identification register. this register is included and contains a revision number, a part number, and a manufacturers identification code specific to conexant (see table 2-7 ). access to this register is through the tap controller through a standard jtag instruction. a variety of verification procedures can be performed through the tap controller. board connectivity can be verified at all digital pins through a set of two instructions accessible through the use of a state machine, standard to all jtag controllers. refer to the ieee std 1149.1 specification for details concerning the instruction register and jtag state machine. a boundary scan description language (bsdl) file for the rs8973 is also available from the factory upon request. table 2-7. jtag device identification register version (1) part number manufacturer id 00000010001100001101000110101 1 0 1 0x0 0x230d (rs8973) 0x0d6 4 bits 16 bits 11 bits note(s): (1) consult factory for current version number. tdo
n8973dsd conexant 3-1 preliminary information 3 3.0 registers 3.1 conventions unless otherwise noted, the following conventions apply to all applicable register descriptions: ? for storage of multiple-bit data fields within a single byte-wide register, the lsbs of the field are located at the lower register-bit positions, whereas the msbs are located at the higher positions. ? if only a single data field is stored in a byte-wide register, the field is justified so that the lsb of the field is located in the lowest register-bit position, bit 0. ? for storage of multiple-byte data words across multiple byte-wide registers, the lsbs of the word are located at the lower byte-address locations, while the msbs are located at the higher byte-address locations. ? when writing to any control or data register with less than all 8-bit positions defined, a logical 0 value must be assigned to each unused/undefined/reserved position. writing a logical 1 value to any of these positions may cause undefined behavior. ? when reading from any control/status or data register with less than all 8-bit positions defined, an indeterminate value is returned from each unused/undefined/reserved position. ? register values are not affected by rst pin assertion, except for the mode bit of the global modes and status register [global_modes; 0x00], the hclk_freq[1,0] field of the serial monitor source select register [serial_monitor_source; 0x01] and the clk_freq[1,0] field of the pll modes register [pll_modes; 0x22]. after rst pin assertion, all device parameters should be reinitialized. ? the initial values of all registers and ram are undefined after power is applied. exceptions include the mode bit of the global modes and status register, the hclk_freq[1,0] field of the serial monitor source select register, the clk_freq[9,8] field of pll modes register, and the clock frequency select register. in addition, the jtag state is reset when power is applied. ? the register and bit mnemonics used here are based on the mnemonics used in the conexant bit pump software. ? writing to unspecified registers may cause unpredictable behavior.
3.0 registers rs8973 3.2 register summary single-chip sdsl/hdsl transceiver 3-2 conexant n8973dsd preliminary information 3 3.0 registers 3.2 register summary table 3-1 displays a summary of the registers. table 3-1. register table (1 of 5) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0 0x00 global_modes r/w hw_revision[3] hw_revision[2] hw_revision[1] hw_revision[0] part_id[2] part_id[1] part_id[0] mode 0x01 serial_monitor_source r/w hclk_freq[1] hclk_freq[0] smon[5] smon[4] smon[3] smon[2] smon[1] smon[0] 0x02 mask_low_reg r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x03 mask_high_reg r/w sync high_felm low_felm low_snr 0x04 timer_source r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x05 irq_source r/w sync high_felm low_felm low_snr 0x06 cu_interface_modes r/w tbclk_pol rbclk_pol fifos_mode interface_mode1 interface_mode[0] 0x07 receive_phase_select r/w imp_short[2] imp_short[1] imp_short[0] rphs[3] rphs[2] rphs[1] rphs[0] 0x08 linear_ec_modes r/w enable_dc_tap adapt_coefficients zero_coefficients zero_output adapt_gain[1] adapt_gain[0] 0x09 nonlinear_ec_modes r/w negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0] adapt_coefficients zero_coefficients zero_outp ut adapt_gain 0x0a dfe_modes r/w adapt_coefficients zero_coefficients zero_output adapt_gain 0x0b transmitter_modes r/w isolated_pulse[1] isolated_pulse[0] transmitter_off htur_lfsr data_source[2] data_source[1] data_source[0] 0x0c timer_restart r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x0d timer_enable r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x0e timer_continuous r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x0f misc_test r/w res[6] res[5] reg_clk_en res[4] res[3] res[2] res[1] async_mode 0x10 sut1_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.2 register summary n8973dsd conexant 3-3 preliminary information 0x11 sut1_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x12 sut2_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x13 sut2_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x14 sut3_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x15 sut3_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x16 sut4_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x17 sut4_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x18 meter_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x19 meter_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x1a snr_timer_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1b snr_timer_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x1c t3_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1d t3_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x1e t4_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1f t4_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x20 clock_freq_select r/w clk_freq[7] clk_freq[6] clk_freq[5] clk_freq[4] clk_freq[3] clk_freq[2] clk_freq[1] clk_freq[0] 0x21 adc_control r/w cont_time[1] cont_time[0] loop_back[1] loop_back[0] switch_cap_pole gain[2] gain[1] gain[0] 0x22 pll_modes r/w clk_freq[9] clk_freq[8] phase_detector_ gain[1] phase_detector_ gain[0] freeze_pll pll_gain[1] pll_gain[0] 0x23 test_reg23 r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x24 pll_phase_offset_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] table 3-1. register table (2 of 5) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
3.0 registers rs8973 3.2 register summary single-chip sdsl/hdsl transceiver 3-4 conexant n8973dsd preliminary information 0x25 pll_phase_offset_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x26 dc_offset_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x27 dc_offset_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x28 tx_calibrate r/w tx_calibrate[3] tx_calibrate[2] tx_calibrate[1] tx_calibrate[0] 0x29 tx_gain r/w tx_gain[3] tx_gain[2] tx_gain[1] tx_gain[0] 0x2a noise_histogram_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x2b noise_histogram_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x2c ep_pause_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x2d ep_pause_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x2e scr_sync_th r/w d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x30 far_end_high_alarm_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x31 far_end_high_alarm_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x32 far_end_low_alarm_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x33 far_end_low_alarm_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x34 snr_alarm_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x35 snr_alarm_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x36 cursor_level_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x37 cursor_level_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x38 dagc_target_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x39 dagc_target_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] table 3-1. register table (3 of 5) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.2 register summary n8973dsd conexant 3-5 preliminary information 0x3a detector_modes r/w enable_peak_ detector output_mux_ control[1] output_mux_ control[0] scr_out_to_dfe two_level lfsr_lock htur_lfsr descr_on 0x3b peak_detector_delay r/w d[3] d[2] d[1] d[0] 0x3c dagc_modes r/w eq_error_ adaption adapt_coefficients adapt_gain 0x3d ffe_modes r/w adapt_last_coeff zero_coefficients adapt_coefficients adapt_gain 0x3e ep_modes r/w zero_output zero_coefficients adapt_coefficients adapt_gain 0x40 pdm_low r/w d[17] d[16] d[15] d[14] d[13] d[12] d[11] d[10] 0x41 pdm_high r/w d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] 0x42 overflow_meter r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x44 dc_meter_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x45 dc_meter_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x46 slm_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x47 slm_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x48 felm_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x49 felm_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x4a noise_histogram_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x4b noise_histogram_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x4c ber_meter_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x4d ber_meter_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x4e symbol_histogram r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] table 3-1. register table (4 of 5) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
3.0 registers rs8973 3.2 register summary single-chip sdsl/hdsl transceiver 3-6 conexant n8973dsd preliminary information 0x50 nlm_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x51 nlm_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x5e pll_frequency_low r/w d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] 0x5f pll_frequency_high r/w d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] 0x70 linear_ec_tap_select_read r/w d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x71 linear_ec_tap_select_write r/w d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x72 nonlinear_ec_tap_select_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x73 nonlinear_ec_tap_select_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x74 dfe_tap_select_read r/w d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x75 dfe_tap_select_write r/w d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x76 sp_tap_select_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x77 sp_tap_select_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x78 eq_add_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x79 eq_add_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x7a eq_microcode_add_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x7b eq_microcode_add_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x7c access_data_byte0 r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x7d access_data_byte1 r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x7e access_data_byte2 r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x7f access_data_byte3 r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] table 3-1. register table (5 of 5) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-7 preliminary information 3 3.3 register description 0x00global modes and status register (global_modes) hw_revision[3:0] chip revision numberread-only unsigned binary field encoded with the chip revision number. smaller values represent earlier versions, while larger values represent later versions. the zero value represents the original prototype release. consult factory for current values and revision. part_id[2:0] part idread-only binary field set to binary 011, identifying the part as rs8973. the following table shows part ids for different dsl transceivers: mode power down moderead/write control bit. when set, stops all filter processing and zeros the transmit output for reduced power consumption. all ram contents are preserved. the mode bit is automatically set by rst assertion and upon initial power application. it can be cleared only by writing a logic 0, at which time filter processing and transmitter operation can proceed. 7 6 5 4 3 2 1 0 hw_revision[3] hw_revision[2] hw_revision[1] hw_revision[0] part_id[2] part_id[1] part_id[0] mode part_id[2] part_id[1] part_id[0] device name 0 0 0 bt8952 0 0 1 bt8960 0 1 0 bt8970 0 1 1 rs8973
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-8 conexant n8973dsd preliminary information 0x01serial monitor source select register (serial_monitor_source) hclk_freq[1,0] hclk frequency selectread/write binary field selects the frequency of the hclk output. smon[5:0] serial monitor source selectread/write binary field selects the serial monitor (smon) output source. 7 6 5 4 3 2 1 0 hclk_freq[1] hclk_freq[0] smon[5] smon[4] smon[3] smon[2] smon[1] smon[0] hclk_freq[1] hclk_freq[0] hclk frequency 0 0 upon assertion of the rst pin and power-on detection, hclk_freq[1,0] is set to 00. symbol frequency (f qclk ) 16. upon assertion of the rst pin and power-on detection, hclk_freq[1,0] is set to 00. 0 1 symbol frequency (f qclk ) 16 1 0 symbol frequency (f qclk ) 32 1 1 symbol frequency (f qclk ) 64 smon[5:0] source decimal binary 0 C 47 00 0000 C 10 1111 equalizer register file 48 11 0000 digital front-end output/is input 49 11 0001 linear echo replica 50 11 0010 dfe subtractor output 51 11 0011 ep subtractor output/slicer input 52 11 0100 timing recovery phase detector output/loop filter input 53 11 0101 timing recovery loop filter output/frequency synthesizer input
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-9 preliminary information 0x02interrupt mask register low (mask_low_reg) independent read/write mask bits for each of the timer source register [timer_source; 0x04] interrupt flags. a logical 1 represents the masked condition. a logical 0 represents the unmasked condition. all mask bits behave identically with respect to their corresponding interrupt flags. setting a mask bit prevents the corresponding interrupt flag from affecting the irq output. clearing a mask allows the interrupt flag to affect irq output. unmasking an active interrupt flag will immediately cause the irq output to go active, if currently inactive. masking an active interrupt flag will cause irq to go inactive, if no other unmasked interrupt flags are set. t4 general purpose timer 4 t3 general purpose timer 3 snr snr alarm timer meter meter timer sut4 startup timer 4 sut3 startup timer 3 sut2 startup timer 2 sut1 startup timer 1 0x03interrupt mask register high (mask_high_reg) independent read/write mask bits for each of the irq source register [irq_source; 0x05] interrupt flags. individual mask bit behavior is identical to that specified for interrupt mask register low [mask_low_reg; 0x02]. sync sync indication high_felm far-end level meter high alarm low_felm far-end level meter high alarm low_snr signal-to-noise ratio low alarm 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 7 6 5 4 3 2 1 0 sync high_felm low_felm low_snr
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-10 conexant n8973dsd preliminary information 0x04timer source register (timer_source) independent read/write (zero only) interrupt flags, one for each of eight internal timers. each flag bit is set and stays set when its corresponding timer value transitions from 1 to 0. if unmasked, this event causes the irq output to be activated. flags are cleared by writing them with a logical 0 value. once a flag is cleared, a steady-state timer value of 0 does not reassert the flag. clearing an unmasked flag causes the irq output to return to the inactive state, if no other unmasked interrupt flags are set. t4 general purpose timer 4 t3 general purpose timer 3 snr snr alarm timer meter meter timer sut4 startup timer 4 sut3 startup timer 3 sut2 startup timer 2 sut1 startup timer 1 0x05irq source register (irq_source) independent read/write (0 only) interrupt flags, one for each of four internal sources. each flag bit is set and stays set when its corresponding source indicates that a valid interrupt condition exists. if unmasked, this event causes the irq output to be activated. writing a logical 0 to an interrupt flag whose underlying condition no longer exists causes the flag to be immediately cleared. attempting to clear a flag whose underlying condition still exists does not immediately clear the flag, but allows it to remain set until the underlying condition expires, at which time the flag is cleared automatically. the clearing of an unmasked flag causes the irq output to return to an inactive state, if no other unmasked interrupt flags are set. sync sync indicationactive when the sync detector is enabled and its accumulated equivalent comparison is greater than the threshold value stored in the scrambler sync threshold register [scr_sync_th; 0x2e]. high_felm far-end level meter high alarmactive when the far-end level meter value is greater than the threshold stored in the far-end high alarm threshold registers [far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30C0x31]. low_felm far-end level meter low alarmactive when the far-end level meter value is less than the threshold stored in the far-end low alarm threshold registers [far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x32C0x33]. low_snr signal-to-noise ratio low alarmactive when the snr alarm meter value is greater than the threshold stored in the snr alarm threshold registers [snr_alarm_th_low, snr_alarm_th_high; 0x34C0x35]. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 7 6 5 4 3 2 1 0 sync high_felm low_felm low_snr
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-11 preliminary information 0x06channel unit interface modes register (cu_interface_modes) tbclk_pol transmit baud clock polarityread/write control bit defines the polarity of the tbclk input while in the parallel slave interface mode. when tbclk_pol is set, tq[1,0] is sampled on the falling edge of tbclk; when cleared, tq[1,0] is sampled on the rising edge. rbclk_pol receive baud clock polarityread/write control bit defines the polarity of the rbclk input while in the parallel slave interface mode. when rbclk_pol is set, rq[1,0] is updated on the falling edge of rbclk; when cleared, rq[1,0] is updated on the rising edge. fifos_mode fifos moderead/write control bit used to stagger the transmit and receive the fifos read and write pointers while in the parallel slave interface mode. a logical 1 forces the pointers to a staggered position; a logical 0 allows them to operate normally. to maximize phase-error tolerance, fifos_mode must be first set, then cleared once after qclk-tbclk-rbclk frequency lock is achieved. interface_ mode[1,0] interface moderead/write binary field specifies one of four operating modes for the channel unit interface. 7 6 5 4 3 2 1 0 tbclk_pol rbclk_pol fifos_mode interface_mode[1] interface_mode[0] interface mode [1:0] mode pin functions 91 90 88 89 85 86 00 parallel masterparallel quat transfer synchronized to qclk out. not used not used rq[1] rq[0] tq[1] tq[0] 01 parallel slaveparallel quat transfer synchronized to separate tbclk and rbclk inputs. tbclk rbclk rq[1] rq[0] tq[1] tq[0] 10 serial, magnitude firstserial quat transfer synchronized to bclk out; magnitude-bit first, followed by sign bit. not used not used rdat bclk tdat not used 11 serial, sign firstserial quat transfer synchronized to bclk out; sign-bit first, followed by magnitude bit. not used not used rdat bclk tdat not used
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-12 conexant n8973dsd preliminary information 0x07receive phase select register (receive_phase_select) imp_short[2:0] impulse shortening filterread/write binary field that determines the coefficient of the impulse shortening filter. it must be set per the software provided by conexant. rphs[3:0] receive phase selectread/write binary field that defines the relative phase relationship between qclk and the sampling point of the adc. the rising edges of qclk correspond to the adc sampling points when rphs equals 0000. each binary increment of rphs represents a one-sixteenth qclk period delay in the sampling point relative to qclk. 0x08linear echo canceller modes register (linear_ec_modes) enable_dc_tap enable dc tapread/write control bit which, when set, forces a constant + 1 value into the last data tap of the lec. this condition enables cancellation of any residual dc offset present at the input to the lec. when cleared, the last data tap operates normally, as the oldest transmit data sample. adapt_coefficents adapt coefficientsread/write control bit which enables coefficient adaptation when set; disables/freezes adaptation when cleared. coefficient values are preserved when adaptation is disabled. zero_coefficients zero coefficientsread/write control bit that continuously zeros all coefficients when set; allows normal coefficient updates if enabled, when cleared. this behavior differs slightly from the similar function (zero_coefficients) of the ffe and ep filters. zero_output zero outputread/write control bit which, when set, zeros the echo replica before subtraction from the input signal. achieves the affect of disabling or bypassing the echo cancellation function. does not disable coefficient adaptation. when cleared, normal echo canceller operation is performed. adapt_gain[1,0] adaptation gainread/write binary field which specifies the adaptation gain. 7 6 5 4 3 2 1 0 imp_short[2] imp_short[1] imp_short[0] rphs[3] rphs[2] rphs[1] rphs[0] 7 6 5 4 3 2 1 0 enable_dc_tap adapt_ coefficients zero_coefficients zero_output adapt_gain[1] adapt_gain[0] adapt_gain[1,0] normalized gain 00 1 01 4 10 64 11 512
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-13 preliminary information 0x09nonlinear echo canceller modes register (nonlinear_ec_modes) negate_symbol negate symbolread/write control bit which, when set, inverts (2s complement) the receive signal path at the output of the nonlinear echo canceller. when cleared, the signal path is unaffected. this function is independent of all other nec mode settings. symbol_delay[2:0] symbol delayread/write binary field which specifies the number of symbol delays inserted in the transmit symbol input path. adapt_coefficients adapt coefficientssame function as lec modes register [linear_ec_modes; 0x08]. zero_coefficients zero coefficientssame function as lec modes register. zero_output zero outputsame function as lec modes register. adapt_gain adaptation gainread/write control bit which specifies the adaptation gain. when adapt_gain is set, the adaptation gain is eight times higher than when cleared. 0x0adecision feedback equalizer modes register (dfe_modes) adapt_coefficents adapt coefficientsread/write control bit which enables coefficient adaptation when set; disables/freezes adaptation when cleared. coefficient values are preserved when adaptation is disabled. zero_coefficients zero coefficientsread/write control bit which continuously zeros all coefficients when set; allows normal coefficient updates, if enabled, when cleared. zero_output zero outputread/write control bit which, when set, zeros the filter output before subtraction from the ffe output. achieves the affect of disabling or bypassing the equalization function. does not disable coefficient adaptation. when cleared, the normal equalizer operation is performed. adapt_gain adaptation gainread/write control bit which specifies the adaptation gain. when adapt_gain is set, the adaptation gain is eight times higher than when cleared. 7 6 5 4 3 2 1 0 negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0] adapt_ coefficients zero_coefficients zero_output adapt_gain 7 6 5 4 3 2 1 0 adapt_ coefficients zero_coefficients zero_output adapt_gain
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-14 conexant n8973dsd preliminary information 0x0btransmitter modes register (transmitter_modes) isolated_pulse[1,0] isolated pulse level selectread/write binary field that selects one of four output pulse levels while in the isolated pulse or alternating symbol transmitter mode. transmitter_off transmitter offread/write control bit that zeros the output of the transmitter when set; allows normal transmitter operation (as defined by data_source[2:0]) when cleared. htur_lfsr remote unit (htu-r/nt) polynomial selectread/write control bit selects one of two feedback polynomials for the transmit scrambler. when set, this bit selects the remote unit transmit polynomial ; when cleared, it selects the local unit (htu-c/lt) polynomial . data_source[2:0] data sourceread/write binary field that selects the data source and mode of the transmitter output. the transmitter must be enabled (transmitter_off = 0) for these modes to be active. 7 6 5 4 3 2 1 0 isolated_pulse[1] isolated_pulse[0] transmitter_off htur_lfsr data_source[2] data_source[1] data_source[0] isolated_pulse[1,0] output pulse level 00 C 3 01 C 1 10 + 3 11 + 1 x 23 C x 18 C 1 ++ () x 23 C x 5 C 1 ++ () data_source [2:0] transmitter mode 000 isolated pulse. level selected by isolated_pulse[1:0]. the meter timer must be enabled and in the continuous mode. the pulse repetition interval is determined by the meter timer countdown interval. 001 four-level scrambled detector loopback. sign and magnitude bits from the receiver detector are scrambled and looped back to the transmitter. feedback polynomial determined by the htur_lfsr control bit. 010 four-level unscrambled data. transmits the four-level (2b1q) sign and magnitude bits from the channel unit transmit interface without scrambling. 011 four-level scrambled 1s. transmits a scrambled, constant high-logic level as a four-level (2b1q) signal. feedback polynomial determined by the htur_lfsr control bit. 100 alternating symbol mode. outputs symbols of alternating polarity. level is selected by isolated_pulse[1:0]. the meter timer must be enabled and in continuous mode. the half period of the output signal is defined by the meter timer countdown interval. 101 four-level scrambled data. scrambles and transmits the four-level (2b1q) sign and magnitude bits from the channel unit transmit interface. feedback polynomial determined by the htur_lfsr control bit. 110 two-level unscrambled data. constantly forces the magnitude bit from the channel unit transmit interface to a logical 0 and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. valid output levels limited to + 3, C 3. 111 two-level scrambled 1s. transmits a scrambled, constant high-logic level as a two-level signal. the feedback polynomial is determined by the htur_lfsr control bit. the scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a constant logical 0. valid output levels are limited to + 3, C 3.
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-15 preliminary information 0x0ctimer restart register (timer_restart) independent read/write restart bits, one for each of the eight internal timers. setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. for the four symbol-rate timers (meter, snr, t3, t4), reloading occurs within 1 symbol period. for the four start-up timers (sut1C4), reloading occurs within 1024 symbol periods. once the timer is reloaded, the restart bit is automatically cleared. if a restart bit is set and then cleared (by writing a logical 0) before the reload actually takes place, no timer reload occurs. once reloaded, if enabled in the timer enable register [timer_enable; 0x0d], the timer begins counting down toward zero; otherwise, it holds at the interval register value. t4 general purpose timer 4 t3 general purpose timer 3 snr snr alarm timer meter meter timer sut4 startup timer 4 sut3 startup timer 3 sut2 startup timer 2 sut1 startup timer 1 0x0dtimer enable register (timer_enable) independent read/write enable bits, one for each of the eight internal timers. when any individual bit is set, the corresponding timer is enabled for counting down from its current value toward 0. for the four symbol-rate timers (meter, snr, t3, t4), counting begins within 1 symbol period. for the four start-up timers (sut1-4), counting begins within 1024 symbol periods. when an enable bit is cleared, the timer is disabled from counting and holds its current value. if an enable bit is set and then cleared before a count actually takes place, no timer countdown occurs. t4 general purpose timer 4 t3 general purpose timer 3 snr snr alarm timer meter meter timer sut4 startup timer 4 sut3 startup timer 3 sut2 startup timer 2 sut1 startup timer 1 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-16 conexant n8973dsd preliminary information 0x0etimer continuous mode register (timer_continuous) independent read/write mode bits, one for each of the eight internal timers. when any individual bit is set, the corresponding timer is placed in the continuous count mode. while in this mode, after reaching the 0 count, an enabled timer will reload the contents of its interval register and continue counting. when a mode bit is cleared, the timer is taken out of the continuous mode. while in this configuration, after reaching the zero count, an enabled timer will simply stop counting and remain at 0. for a description of bit-fields, refer to the description given above for register 0x0dtimer enable register (timer_enable) . 0x0fmiscellaneous/test register (misc_test) a 1-byte read/write register that is automatically initialized to 0x00 upon rst assertion and initial power application. res[6:1] reserved bitsread/write binary field that is automatically initialized to 0x00 upon rst assertion and initial power application. reg_clk_en regenerator clock enablewhen set, it bypasses the frequency synthesizer and timing recovery. in this mode, the symbol rate equals mclk 16. normally this bit is reset and should be set only for the transceiver configured as regCc in a regenerator configuration. refer to section 1.3, regenerator configuration . async_mode asynchronous moderead/write control bit that selects asynchronous mci timing mode, when set. when reset it selects synchronous mode mci timing. refer to table 5-13, microcomputer interface timing requirements , and table 5-14, microcomputer interface switching characteristics , for mci timing requirements and switching characteristics. 0x10, 0x11startup timer 1 interval register (sut1_low, sut1_high) a 2-byte read/write register that stores the countdown interval for startup timer 1 in unsigned binary format. each increment represents 1024 symbol periods. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 0x12, 0x13startup timer 2 interval register (sut2_low, sut2_high) a 2-byte read/write register that stores the countdown interval for startup timer 2 in unsigned binary format. each increment represents 1024 symbol periods. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 7 6 5 4 3 2 1 0 res[6] res[5] reg_clk_en res[4] res[3] res[2] res[1] async_mode
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-17 preliminary information 0x14, 0x15startup timer 3 interval register (sut3_low, sut3_high) a 2-byte read/write register that stores the countdown interval for startup timer 3 in unsigned binary format. each increment represents 1024 symbol periods. the contents of this register are automatically loaded into its associated timer after the timer_restart bit is set, or after the timer counts down to zero while in the continuous mode. 0x16, 0x17startup timer 4 interval register (sut4_low, sut4_high) a 2-byte read/write register that stores the countdown interval for startup timer 4 in unsigned binary format. each increment represents 1024 symbol periods. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 0x18, 0x19meter timer interval register (meter_low, meter_high) a 2-byte read/write register that stores the countdown interval for the meter timer in unsigned binary format. each increment represents one symbol period. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 0x1a, 0x1bsnr alarm timer interval register (snr_timer_low, snr_timer_high) a 2-byte read/write register that stores the countdown interval for the snr alarm timer in unsigned binary format. each increment represents one symbol period. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 0x1c, 0x1dgeneral purpose timer 3 interval register (t3_low, t3_high) a 2-byte read/write register that stores the countdown interval for general purpose timer 3 in unsigned binary format. each increment represents one symbol period. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 0x1e, 0x1fgeneral purpose timer 4 interval register (t4_low, t4_high) a 2-byte read/write register that stores the countdown interval for general purpose timer 4 in unsigned binary format. each increment represents one symbol period. the contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode.
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-18 conexant n8973dsd preliminary information 0x20clock frequency select register (clock_freq_select) clk_freq[7:0] read/write binary field, which along with clk_freq[9,8] of the pll modes register (0x22), specifies the data rate used by the clock synthesizer to generate the appropriate internal clock. clk_freq = 18 to 290 data rate = clk_freq 8 kbps (144 kbps to 2320 kbps) the power-on default is clk_freq = 0 which selects the internal clock corresponding to 1280 kbps. 0x21adc control register (adc_control) cont_time[1,0] continuous time controlread/write binary field that controls the cut-off frequency of the analog rc reconstruction filter, according to the data rates. the 00 setting of the continuous_time control bits enables an output pulse shape that conforms to the etsi hdsl specifications at 1168 kbps. the 01 setting enables an output pulse shape that conforms to the ansi and etsi hdsl specifications at 784 kbps. the 10 setting enables an output pulse shape that conforms to the etsi hdsl specifications at 2320 kbps. loop_back[1,0] loopback controlread/write binary field that specifies if loopback is enabled, and the type of loopback that is enabled. during transmitting loopback, the differential receiver inputs (rxp, rxn) are disabled. the loopback path is intended to go from the transmitter outputs (txp, txn) through the external hybrid circuit and back into the differential receiver balance inputs (rxbp, rxbn). during silent loopback, the transmitter is turned off. the output of the pulse-shaping filter in the transmit section is internally connected to the input of the adc in the receive section. 7 6 5 4 3 2 1 0 clk_freq[7] clk_freq[6] clk_freq[5] clk_freq[4] clk_freq[3] clk_freq[2] clk_freq[1] clk_freq[0] 7 6 5 4 3 2 1 0 cont_time[1] cont_time[0] loop_back[1] loop_back[0] switch_cap_pole gain[2] gain[1] gain[0] cont_time[1,0] data rate range 00 800 to 1200 kbps 01 less than 800 kbps 10 above 1200 kbps 11 reserved loop_back[1,0] function 00 normal operation (loopback disabled) 01 hybrid inputs disabled (rxbp, rxbn) 10 transmitting loopback 11 silent loopback
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-19 preliminary information switch_cap_pole switch cap pole controlread/write control bit, specifies the pulse shaping filter characteristics. when switch_cap_pole is set, it enables output pulse shape conforming to etsi specifications for 2320 kbps operation. when reset, it enables output pulse shape for other data rates. gain[2:0] gain controlread/write binary field that specifies the gain of the vga. 0x22pll modes register (pll_modes) clk_freq[9,8] clock frequency selectsee description for 0x20clock frequency select register (clock_freq_select) . phase_detector_ gain[1,0] phase detector gainread/write binary field that specifies one of three gain settings for the timing-recovery phase detector function. freeze_pll freeze pllread/write control bit. when set, this bit zeros the proportional term of the loop compensation filter and disables accumulator updates, causing the pll to hold its current frequency. when this bit is cleared, proportional term effects and accumulator updates are enabled, allowing the pll to track the phase of the incoming data. pll_gain[1,0] pll gainread/write binary field that specifies the gain (proportional and integral coefficients) of the loop compensation filter. gain[2:0] vga gain 000 0 db 001 3 db 010 6 db 011 9 db 100 12 db 101 15 db 110 15 db 111 15 db 7 6 5 4 3 2 1 0 clk_freq[9] clk_freq[8] phase_detector_ gain[1] phase_detector_ gain[0] freeze_pll pll_gain[1] pll_gain[0] phase_detector_gain[1,0] normalized gain 00 1 01 2 10 4 11 reserved pll_gain[1:0] normalized proportional coefficients normalized integral coefficients 00 1 1 01 4 32 10 16 256 11 64 4096
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-20 conexant n8973dsd preliminary information 0x23test register (test_reg23) a 3-byte read/write register used for device testing by conexant. this register is automatically initialized to 0x000000 upon rst assertion and initial power application. this register must be initialized according to the software provided by conexant. 0x24, 0x25timing recovery pll phase offset register (pll_phase_offset_low, pll_phase_offset_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the value of this register is subtracted from the output of the timing-recovery phase detector after the phase-detector meter, but before the loop compensation filter. 0x26, 0x27receiver dc offset register (dc_offset_low, dc_offset_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the value of this register is subtracted from the receiver signal path at the output of the adc block, ahead of the dc level and signal level meters. 0x28transmitter calibration register (tx_calibrate) tx_calibrate[3:0] transmit calibrate4-bit, 2s-complement, read-only field containing the nominal setting for the transmitter gain. the value of the transmit calibration register is set during manufacturing testing by conexant, and corresponds to the value required to operate the rs8973 at a nominal 13.5 dbm transmit power, assuming the recommended transformer coupling/hybrid circuit is used. users can override this calibration by writing their own value into the transmitter gain register [tx_gain; 0x29]. 7 6 5 4 3 2 1 0 tx_calibrate[3] tx_calibrate[2] tx_calibrate[1] tx_calibrate[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-21 preliminary information 0x29transmitter gain register (tx_gain) tx_gain[3:0] transmit gaina 4-bit, 2s-complement, read/write field controlling the transmitter gain. upon initialization, the value in the transmitter calibration register [tx_calibrate; 0x28] can be written into this register by software, to set the transmitter gain to the nominal value. alternatively, the user can set it to another desired value. the transmitter gain settings are relative to the setting that provides a nominal output power of 13.5 dbm. 0x2a, 0x2bnoise-level histogram threshold register (noise_histogram_th_low, noise_histogram_th_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x7fff. the value of this register is compared to the absolute value of the slicer error signal produced by the detector. a count of error samples that exceeds this threshold (greater than) is accumulated in the noise-level histogram meter. 0x2c, 0x2derror predictor pause threshold register (ep_pause_th_low, ep_pause_th_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x7fff. the value of this register is compared to the absolute value of the slicer error signal produced by the detector. the result of this comparison (slicer error greater than this threshold) is used to initiate a pause condition by zeroing the output of the error predictor correction signal before subtraction from the receive signal path. error predictor coefficient updates are not affected. the pause condition lasts for a fixed 5-symbol period from the time the threshold was last exceeded. 7 6 5 4 3 2 1 0 tx_gain[3] tx_gain[2] tx_gain[1] tx_gain[0] tx_gain[3:0] relative transmitter gain (db) 1000 C1.60 1001 C1.36 1010 C1.13 1011 C0.91 1100 C0.69 1101 C0.48 1110 C0.27 1111 C0.07 0000 0.13 0001 0.32 0010 0.51 0011 0.70 0100 0.88 0101 1.05 0110 1.23 0111 1.40
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-22 conexant n8973dsd preliminary information 0x2escrambler synchronization threshold register (scr_sync_th) a 7-bit read/write register representing an unsigned binary number. the contents of this register are used to test for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector. the test passes when the count of equivalent scrambler and detector output bits is greater than the value of this register. when the auto-scrambler sync mode is not enabled, the contents of this register are not used. 0x30, 0x31far-end high alarm threshold register (far_end_high_alarm_th_low, far_end_high_alarm_th_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x7fff. the value of this register is compared to the value of the far-end level meter. if the meter reading is greater than this threshold, the high_felm interrupt flag is set in the irq source register [irq_source; 0x05]. 0x32, 0x33far-end low alarm threshold register (far_end_low_alarm_th_low, far_end_low_alarm_th_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x7fff. the value of this register is compared to the value of the far-end level meter. if the meter reading is less than this threshold, the low_felm interrupt flag is set in the irq source register [irq_source; 0x05]. 0x34, 0x35snr alarm threshold register (snr_alarm_th_low, snr_alarm_th_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x7fff. the value of this register is compared to the value of the snr alarm meter. if the meter reading is greater than this threshold, the low_snr interrupt flag is set in the irq source register [irq_source; 0x05]. 0x36, 0x37cursor level register (cursor_level_low, cursor_level_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x2aaa (one-third of the maximum positive value). the value of this register represents the expected level of a noise-free + 1 receive symbol at the slicer input. it is multiplied by 2 to produce the positive and negative slicing levels, in addition to 0, used by the symbol detector in four-level slicing mode. this value is also used to scale the detector output when computing the equalizer error and slicer error signals. the detected symbol (C 3, C 1, + 1, + 3) is multiplied by the value of this register to produce the scaled output. 0x38, 0x39dagc target register (dagc_target_low, dagc_target_high) a 2-byte read/write register interpreted as a 16-bit, 2s-complement number. the range of meaningful values is limited to positive integers between 0x0000 and 0x7fff. the value of this register is subtracted from the absolute value of the receive signal at the output of the dagc function. the difference is used as the error input to the dagc while in the self-adaptation mode. in the dagcs equalizer-error adaptation mode, the contents of this register are not used. 7 6 5 4 3 2 1 0 d[6] d[5] d[4] d[3] d[2] d[1] d[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-23 preliminary information 0x3asymbol detector modes register (detector_modes) enable_peak_ detector enable peak detectorread/write control bit that enables the peak detection function when set; disables the function when cleared. when enabled, the peak detector output overrides the slicer output if the peak detection criteria are met. if the criteria are not met, or if the function is disabled, the slicer output is used and peak detector output is ignored. output_mux_ control[1,0] output multiplexer controlread/write binary field that selects the source of the detector output connected to the channel unit receive interface. scr_out_to_dfe scrambler output to dferead/write control bit that selects the source of the detector output connected to the dfe and timing recovery module inputs and the transmitters detector loopback input. when set, this bit selects the scrambler/descrambler function; when cleared, it selects the slicer/peak detector output. two_level two-level moderead/write control bit that selects two-level mode when set, four-level mode when cleared. affects the slicer and the scrambler/descrambler function. in two-level mode, the slicer uses a single threshold set at zero to recover sign bits only; all magnitude information is lost. scrambler/descrambler updates are slowed to the symbol rate (half the normal bit rate) to process only sign information as well; all magnitude output bits are sourced with a constant logic zero value, producing two-level symbols constrained to +3 and C3 values. in four-level mode, the slicer uses two thresholds derived from the cursor level register [cursor_level_low, cursor_level_high; 0x36C0x37], as well as the zero threshold, to recover both sign and magnitude information. the scrambler/descrambler is updated at the full bit rate to process both sign and magnitude bits as well. 7 6 5 4 3 2 1 0 enable_peak_ detector output_mux_ control[1] output_mux_ control[0] scr_out_to_dfe two_level lfsr_lock htur_lfsr descr_on output_mux_control[1,0] detector output to cu receive interface 00 same as scr_out_to_dfe selection 01 transmitter loopback output from cu transmit interface 10 scrambler/descrambler output 11 reserved
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-24 conexant n8973dsd preliminary information lfsr_lock lfsr lockread/write control bit that enables the auto-scrambler synchronization mode (lfsr_lock) in the detector when set and disables this mode when cleared. affects the behavior of the scrambler/descrambler function, overriding the descr_on setting. when enabled, the scrambler/descrambler is forced into the descrambler mode for 23 cycles. it is then switched to the scrambled-1s mode for 128 cycles. while in this mode, the outputs of the scrambler and the slicer/peak detector are compared against one another. the number of equivalent bits (equal comparisons) is accumulated and compared to the value of the scrambler synchronization threshold register [scr_sync_th; 0x2e]. at any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync interrupt flag is set in the irq source register [irq_source; 0x05] and the process terminates with the scrambler/descrambler left in the scrambled-1s mode. (the sync interrupt flag cannot be cleared while lfsr_lock remains high.) after 128 cycles, if the threshold is not exceeded, the accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another 23 cycles, and the process repeats until either sync is achieved or this mode is disabled. once disabled, the sync interrupt flag can be cleared (if active) and the scrambler/descrambler returns to the mode specified by descr_on. htur_lfsr remote unit (htu-r/nt) polynomial selectread/write control bit that selects one of two feedback polynomials for the scrambler/descrambler. when set, this bit selects the remote unit (htu-r/nt) receive polynomial (x C 23 + x C 5 + 1); when cleared, it selects the local unit (htu-c/lt) polynomial (x C 23 + x C 18 + 1). descr_on descrambler/scrambler selectread/write control bit that configures the scrambler/descrambler function as a descrambler when set, and as a scrambler when cleared. as a scrambler, this bit enables the scrambler/descrambler to generate a scrambled-all-1s sequence (constant high logic-level input); all incoming data is ignored. in the auto-scrambler synchronization mode (lfsr_lock = 1), this selection is overwritten though the value of the control bit is unaffected. 0x3bpeak detector delay register (peak_detector_delay) a 4-bit read/write register interpreted as an unsigned binary number. specifies a number of additional symbol delays inserted in the peak detector input path of the symbol detector. must be set to a value that equalizes the total path delay in each of the peak detector and slicer input paths according to the following formula: peak detector delay register value = dagc delays + ffe delays C fixed peak detector input delays. the dagc and ffe delays are not fixed, but result from the microprogrammed implementation of these functions. the value should be set according to software supplied by conexant. 7 6 5 4 3 2 1 0 d[3] d[2] d[1] d[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-25 preliminary information 0x3cdigital agc modes register (dagc_modes) eq_error_ adaptation equalizer error adaptationread/write control bit that selects between the equalizer-error adaptation mode when set, and the self-adaptation mode when cleared. equalizer error adaptation uses the equalizer error signal produced by the slicer as the dagc error input signal. in self-adaptation, the value of the dagc target register [dagc_target_low, dagc_target_high; 0x38C0x39] is subtracted from the absolute value of the receive signal at the output of the dagc, and this difference is used as the error input signal. adapt_coefficients adapt coefficientsread/write control bit that enables coefficient adaptation when set; disables/freezes adaptation when cleared. coefficient values are preserved when adaptation is disabled. adapt_gain adaptation gainread/write control bit that specifies the adaptation gain. when this bit is set, the adaptation gain is eight times higher than when cleared. 0x3dfeed forward equalizer modes register (ffe_modes) adapt_last_coeff adapt last coefficientread/write control bit that enables adaptation of the last (oldest) coefficient only when set; allows all coefficient adaptation when cleared. overall coefficient adaptation must be enabled (adapt_coefficients = 1) for this behavior to occur. if coefficient adaptation is disabled (adapt_coefficients = 0), the value of this control bit is not used. zero_coefficients zero coefficientsread/write control bit that, with coefficient adaptation enabled (adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal coefficient updates when cleared. if coefficient adaptation is disabled (adapt_coefficients = 0), this control bit has no affect. this behavior differs slightly from the similar function (zero_coefficients) of the lec, nec, and dfe filters. whenever this bit is set, it must be accompanied by adapt_coefficients (set) for a 2-symbol time period. adapt_coefficents adapt coefficientsread/write control bit that enables coefficient adaptation when set; disables/freezes adaptation when cleared. coefficient values are preserved when adaptation is disabled. this overall coefficient adaptation must be enabled for adapt_last_coeff to have an affect. adapt_gain adaptation gainread/write control bit that specifies the adaptation gain. when set, the adaptation gain is four times higher than when cleared. 7 6 5 4 3 2 1 0 eq_error_ adaptation adapt_coefficients adapt_gain 7 6 5 4 3 2 1 0 adapt_last_coeff zero_coefficents adapt_ coefficients adapt_gain
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-26 conexant n8973dsd preliminary information 0x3eerror predictor modes register (ep_modes) zero_output zero outputread/write control bit that, when set, zeros the error predictor correction signal before subtraction at the slicer. achieves the affect of disabling, or bypassing, the error predictor function. does not disable coefficient adaptation. when cleared, normal error predictor operation is performed. zero_coefficients zero coefficientsread/write control bit that, with coefficient adaptation enabled (adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal coefficient updates when cleared. if coefficient adaptation is disabled (adapt_coefficients = 0), this control bit has no affect. this behavior differs slightly from the similar function (zero_coefficients) of the lec, nec, and dfe filters. whenever this bit is set, it must be accompanied by adapt_coefficients (set) for a 2-symbol time period. adapt_coefficents adapt coefficientsread/write control bit that enables coefficient adaptation when set and disables/freezes adaptation when cleared. coefficient values are preserved when adaptation is disabled. adapt_gain adaptation gainread/write control bit that specifies the adaptation gain. when this bit is set, the adaptation gain is four times higher than when cleared. 0x40, 0x41phase detector meter register (pdm_low, pdm_high) a 2-byte read-only register containing the 16 msbs of the 26-bit, 2s-complement phase detector meter accumulator. this meter sums the output of the timing recovery modules phase detector over each meter timer countdown interval, before being offset by the phase offset register [pll_phase_offset_low, pll_phase_offset_high; 0x24, 0x25]. automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 0x42overflow meter register (overflow_meter) a single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. this meter counts the number of adc overflow conditions which occur during each meter timer countdown interval, limited to a maximum count of 255 (0xff). the meter register is automatically loaded at the end of each countdown interval. 7 6 5 4 3 2 1 0 zero_output zero_coefficients adapt_ coefficients adapt_gain 7 6 5 4 3 2 1 0 d[17] d[16] d[15] d[14] d[13] d[12] d[11] d[10] d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-27 preliminary information 0x44, 0x45dc level meter register (dc_meter_low, dc_meter_high) a 2-byte read-only register containing the 16 msbs of the 32-bit, 2s-complement dc-level meter accumulator. this meter sums the value of the receive signal input pathafter dc offset correction but before echo cancellationover each meter timer countdown interval. automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 0x46, 0x47signal level meter register (slm_low, slm_high) a 2-byte read-only register containing 16 msbs of the 32-bit unsigned signal-level meter accumulator. this meter sums the absolute value of the receive signal input pathafter dc offset correction but before echo cancellation (same point as the dc level meter)over each meter timer countdown interval. automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 0x48, 0x49far-end level meter register (felm_low, felm_high) a 2-byte read-only register containing 16 msbs of the 32-bit unsigned far-end level meter accumulator. this meter sums the absolute value of the receive signal pathafter echo cancellation but before the dagc functionover each meter timer countdown interval. automatically loaded at the end of each interval, this meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24]
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-28 conexant n8973dsd preliminary information 0x4a, 0x4bnoise level histogram meter register (noise_histogram_low, noise_histogram_high) a 2-byte read-only register containing all 16 bits of the unsigned noise-level histogram meter accumulator. this meter counts the number of high-noise-level conditions which occur during each meter timer countdown interval. a high-noise-level condition is defined as the absolute value of the slicer error signal exceeding (greater than) the threshold specified in the noise-level histogram threshold register [0x2a, 2b]. automatically loaded at the end of each countdown interval, this meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 0x4c, 0x4dbit error rate meter register (ber_meter_low, ber_meter_high) a 2-byte read-only register containing all 16 bits of the unsigned ber meter accumulator. this meter counts the number of error-free bits recovered by the detector during each meter timer countdown interval. an error-free bit is defined as a match (equal comparison) of the detectors slicer/peak detector output and its scrambler/descrambler output, when operating as a scrambler. when the scrambler/descrambler is operated as a descrambler, the meter simply counts the number of logical 1s produced by the descrambler. the meter register is automatically loaded at the end of each countdown interval, and must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 0x4esymbol histogram meter register (symbol_histogram) a single-byte read-only register containing 8 msbs of the 16-bit unsigned symbol histogram meter accumulator. this meter counts the number of + 1 or C 1 symbols detected during each meter timer countdown interval. no increment occurs when a + 3 or C 3 symbol is detected. the meter register is automatically loaded at the end of each countdown interval. 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-29 preliminary information 0x50, 0x51noise level meter register (nlm_low, nlm_high) a 2-byte read-only register containing 16 msbs of the 32-bit unsigned noise-level meter accumulator. this meter sums the absolute value of the detectors slicer-error signal over each meter timer countdown interval. automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). 0x5e, 0x5f pll frequency register (pll_frequency_low, pll_frequency_high) a 2-byte read/write register comprising 16 msbs of the 31-bit, 2s-complement timing recovery loop compensation filter accumulator. treated much like a meter register, the frequency register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5f). writes must occur in the same order, with the low byte written first, followed by the high byte. write accesses can be separated by any number of other read or write accesses. 0x70lec read tap select register (linear_ec_tap_select_read) a 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal. when written, it causes the selected 32-bit coefficient of the lec to be subsequently loaded into the access data register [access_data_byte[3:0]; 0x7cC0x7f] within 2 symbol periods. does not affect the value of the coefficient. no other data access should occur between the time the read tap select register is written and the time the access data register is read, or the data may be corrupted. 0x71lec write tap select register (linear_ec_tap_select_write) a 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal. when written, it causes all 32 bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] to be subsequently written to the selected lec coefficient within 2 symbol periods. does not affect the value of the access data register. 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 7 6 5 4 3 2 1 0 d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] 7 6 5 4 3 2 1 0 d[6] d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[6] d[5] d[4] d[3] d[2] d[1] d[0]
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-30 conexant n8973dsd preliminary information 0x72nec read tap select register (nonlinear_ec_tap_select_read) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal. when written, this register causes the selected 14-bit coefficient of the nec to be subsequently loaded into the lowest-order bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] within 2 symbol periods. does not affect the value of the coefficient. no other data access should occur between the time the read tap select register is written and the time the access data register is read, or the data may be corrupted. 0x73nec write tap select register (nonlinear_ec_tap_select_write) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal. when written, this register causes the lowest-order 14 bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] to be subsequently written to the selected nec coefficient within 2 symbol periods. does not affect the value of the access data register. 0x74dfe read tap select register (dfe_tap_select_read) a 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 115 decimal. when written, this register causes the selected 16-bit coefficient of the dfe to be subsequently loaded into the lowest-order bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] within 2 symbol periods. does not affect the value of the coefficient. no other data access should occur between the time the read tap select register is written and the time the access data register is read, or the data may be corrupted. 0x75dfe write tap select register (dfe_tap_select_write) a 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 115 decimal. when written, this register causes the lowest-order 16 bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] to be subsequently written to the selected dfe coefficient within 2 symbol periods. does not affect the value of the access data register. 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[6] d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[6] d[5] d[4] d[3] d[2] d[1] d[0]
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-31 preliminary information 0x76scratch pad read tap select (sp_tap_select_read) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal. when written, this register causes the selected 8-bit scratch pad memory location to be subsequently loaded into the lowest-order bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] within 2 symbol periods. does not affect the value of the memory. no other data access should occur between the time the read tap select register is written and the time the access data register is read, or the data may be corrupted. 0x77scratch pad write tap select (sp_tap_select_write) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal. when written, this register causes the lowest-order 8 bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] to be subsequently written to the selected scratch pad memory location within 2 symbol periods. does not affect the value of the access data register. 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0]
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-32 conexant n8973dsd preliminary information 0x78equalizer read select register (eq_add_read) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimal. when written, this register causes the selected 16-bit location of the equalizer register file to be subsequently loaded into the lowest-order bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] within 2 symbol periods. does not affect the value of the register file location. an address map of the shared register file, as defined by the factory-delivered microcode, is displayed in table 3-2 . no other data access should occur between the time the read tap select register is written and the time the access data register is read, or the data may be corrupted. 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] table 3-2. address map of shared register fill d[5:0] stored parameter decimal binary 0C7 00 0000C00 0111 ffe coefficients 0C7 8C15 00 1000C00 1111 ffe data taps 0C7 16C20 01 0000C01 0100 ep coefficients 0C4 21C25 01 0101C01 1001 ep data taps 0C4 26 01 1010 dagc gainleast-significant word 27 01 1011 dagc gainmost-significant word 28 01 1100 dagc output 29 01 1101 ffe output 30 01 1110 dagc input 31 01 1111 ffe output, delayed 1 symbol period 32 10 0000 dagc error signal 33 10 0001 equalizer error signal 34 10 0010 slicer error signal 35C47 10 0011C10 1111 reserved
rs8973 3.0 registers single-chip sdsl/hdsl transceiver 3.3 register description n8973dsd conexant 3-33 preliminary information 0x79equalizer write select register (eq_add_write) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimal. when written, this register causes the lowest-order 16 bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] to be subsequently written to the selected equalizer register file location within 2 symbol periods. does not affect the value of the access data register. an address map of the shared register file, as defined by the factory-delivered microcode, is displayed in table 3-2, address map of shared register fill . 0x7aequalizer microcode read select register (eq_microcode_add_read) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal. when written, this register causes the selected 32-bit location of the equalizer microprogram store to be subsequently loaded into the access data register [access_data_byte[3:0]; 0x7cC0x7f] within 2 symbol periods. does not affect the value of the microprogram store location. no other data access should occur between the time the read tap select register is written and the time the access data register is read, or the data may be corrupted. 0x7bequalizer microcode write select register (eq_microcode_add_write) a 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal. when written, this register causes all 32 bits of the access data register [access_data_byte[3:0]; 0x7cC0x7f] to be subsequently written to the selected equalizer microprogram store location within 2 symbol periods. does not affect the value of the access data register. a factory-developed equalizer microcode is included with the no-fee licensed hdsl transceiver software available from conexant. 0x7cC0x7faccess data register (access_data_byte3:0) a 4-byte read/write register that stores filter coefficient, equalizer register file, and equalizer microprogram store contents during indirect accesses to these ram-based locations. writes to addresses 0x70 through 0x7b, and uses the contents of this shared register as specified in each of the individual register descriptions. 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0]
3.0 registers rs8973 3.3 register description single-chip sdsl/hdsl transceiver 3-34 conexant n8973dsd preliminary information
n8973dsd conexant 4-1 preliminary information 4 4.0 interconnection information note: this section replaces the rs8973 application note (n8973an1a). the configuration described in this section supports data rates ranging from 144 kbps and 2320 kbps, with the output signal conforming to ets ts 101 135 (formerly etr 152) specifications for pulse-shape, power spectral density and output power at 784 kbps, 1168 kbps, and 2320 kbps. four types of interconnections are discussed: 1. transmission line interface, including the compromise hybrid 2. dc blocking capacitor 3. voltage reference and compensation circuitry 4. crystal/clock interface
4.0 interconnection information rs8973 4.1 transmission line interface single-chip sdsl/hdsl transceiver 4-2 conexant n8973dsd preliminary information 4.1 transmission line interface the transmission line interface consists of the compromise hybrid, two impedance matching resistors and the line transformer. figure 4-1, line interface interconnection diagram , illustrates the interconnections. figure 4-1. line interface interconnection diagram 1:2 rxp (77) rxn (78) txp (71) txn (74) rxbp (79) rxbn (80) c5 r7 r8 15.4 w 15.4 w c1 r1 c2 r2 c6 r10 r3 c3 r4 c4 r5 r6 r9 primary secondary l compromise hybrid circuit antialiasing filter antialiasing filter line transformer matching resistors r11 r12 line c10 8973_038 surge protection surge protection surge protection
rs8973 4.0 interconnection information single-chip sdsl/hdsl transceiver 4.1 transmission line interface n8973dsd conexant 4-3 preliminary information 4.1.1 compromise hybrid the purpose of the compromise hybrid is to model the impedance of the transmission line. this model generates an approximation of the transmitted signals echo. the echo replica is then subtracted from the signal on the line transformer to generate a first order approximation of the received signal. the rs8973 includes a dual differential analog input to accommodate a hybrid using only passive components. hybrid component values have been determined by means of calculations and simulations that optimize the echo cancellation functions at the frequencies of interest for the loops as specified in the ets ts 101 135 (formerly etr 152) standards. in addition, maximum reach was taken into consideration for the hybrid design. to maximize digital echo cancellation within the rs8973, it is important that the compromise hybrid transfer function be highly linear. therefore, we recommend that all capacitors used in the hybrid be npo ceramic capacitors because of their highly linear characteristics. although the rs8973 contains a digital echo canceller (ec), the hybrid is needed to reduce the signal level input to the adc. this eliminates adc overflow for short loops and increases the resolution of the digitized receive signal for better digital signal processing performance. in addition, because the digital ec cannot cancel out very low frequency signals, it is very important that the analog ec cancel out most of the low frequency echo. table 4-1 lists compromise hybrid component values. note: all capacitors in the signal path should be film or npo ceramic capacitors. table 4-1. compromise hybrid component values hybrid components value r1, r4 1.58 k w c1, c4 2.3 nf r2, r3 2.0 k w c2, c3 1 nf r5, r6 6.04 k w r11, r12 5.1 k w
4.0 interconnection information rs8973 4.1 transmission line interface single-chip sdsl/hdsl transceiver 4-4 conexant n8973dsd preliminary information 4.1.2 impedance-matching resistors impedance-matching resistors are placed in the transmit path so that the output impedance of the line interface more closely matches the impedance of the transmission line and load. this maximizes the power transferred to the receiver on the other end of the line. the load is assumed to be 135 w . anti-aliasing filters are built on-chip to filter out high frequencies that would be aliased back into the passband as noise. these filters can be made of all passive components. the cutoff frequency (fc) should be as low as possible to achieve maximum attenuation of aliasing frequencies without filtering out the desired signal. because the highest frequency in the desired signal is equal to one-half of the symbol rate, there should be no more than 1 db of attenuation at this frequency. table 4-2 lists the component values recommended for the antialiasing filters. note that the other components in the hybrid affect the frequency response of the antialiasing filters. 4.1.3 line transformer the line transformer provides dc isolation from the transmission line by creating a high-pass filter. the winding ratio of the transformer must be 2:1 (line side:circuit side) to generate the appropriate voltage level on the line. the primary inductance (l) of the transformer (line side) is a very critical parameter. if l is too high, the cutoff frequency of the filter will be too low and the rs8973 echo canceller and equalizer will not be able to cancel out the low frequency components of the echo and inter-symbol interference. if l is too low, part of the information in the signal will be filtered out, thereby decreasing the snr ratio. in addition, the line transformer must meet other requirements to maximize system performance. see table 4-3 for line transformer requirements. table 4-4 lists additional requirements that may be needed to specify the line transformer, depending upon the application in which it is to be used. these requirements have been submitted to several transformer vendors to expedite the development process. a list of these transformer vendors along with their associated transformer part numbers is listed in table 4-5 . these requirements may need to be modified to match the needs of a specific system. for example, if remote line powering is being used, the transformer must operate under a fairly high dc current condition. the exact current specification will depend on several factors including the voltage provided over the line, and the power consumption at the remote end. the application-specific requirements should be reviewed to ensure the transformer is not under- or over-specified. an over-specified transformer may unnecessarily increase cost, while an under-specified transformer may not perform adequately under all system conditions. table 4-2. antialias filter component values antialias filter components value r7, r8 1 k w c5 56pf r9, r10 1 k w c6 56 pf
rs8973 4.0 interconnection information single-chip sdsl/hdsl transceiver 4.1 transmission line interface n8973dsd conexant 4-5 preliminary information table 4-3. line transformer specifications parameter value turns ratio (1) 2:1 (2%) primary inductance (2) 2 mh (10%) return loss (mid-band) 16 db (40 to 300 khz) return loss (low-band) C20 db/decade (below 40 khz) return loss (high-band) C20 db/decade (above 300 khz) longitudinal balance (low-band) 53 db (0.5 to 300 khz) longitudinal balance (high band) C20 db/decade (above 300 khz) insertion loss 0.5 db at 40 khz frequency response 0.1 db (36 to 580 khz) total harmonic distortion (3) C70 db at 36 khz note(s): (1) turns ratio is specified line side to circuit side (line side:circuit side). the line side windings are usually split to accomm odate a dc blocking capacitor. (2) the primary inductance is for the line side of the transformer. (3) test condition: 14 dbm on line side (135 w load) with dc current present (if applicable). table 4-4. line transformer application-specific specifications parameter requirement operating temperature range C40 c to +85 c dc current 60 ma dielectric strength 1500 vdc / 3000 vac creepage and clearance table 4-5. recommended line transformer suppliers supplier name and address supplier phone number(s) part number midcom, inc. p.o. box 1330 watertown, sd 57201 (800) 643-2661 (605) 886-4385 50050 pulse engineering application engineering 1220 world trade dr. san diego, ca 92128 (619) 674-8100 schott corporation 1000 parkers lake rd minneapolis, mn 55391 (612) 475-1173
4.0 interconnection information rs8973 4.2 dc blocking capacitor single-chip sdsl/hdsl transceiver 4-6 conexant n8973dsd preliminary information 4.2 dc blocking capacitor a dc blocking capacitor is placed in series with the center split primary winding (line side) of the line transformer to facilitate remote power feed or injection of sealing current. see table 4-6 . 4.3 voltage reference and compensation circuitry compensation capacitors must be connected between all of the rs8973 voltage reference pins and analog ground. the voltage reference signals, their associated pin numbers, and the recommended compensation capacitor values are listed in table 4-7 . in addition to the compensation capacitors, an external resistor is needed to set the bias current used in the rs8973. this resistor must be connected between the rbias pin (pin 56) and analog ground. the recommended value of the resistor is given in table 4-8 . table 4-6. dc blocking capacitor value component value c10 1 m f table 4-7. compensation capacitor values signal name pin number capacitor value vcomo 58 0.22 m f vcomi 57 0.22 m f vccap 59 0.22 m f vrxp 51 0.22 m f vrxn 52 0.22 m f vtxp 60 0.22 m f vtxn 61 0.22 m f table 4-8. bias current resistor value signal name pin number resistor value rbias 56 9.53 k w
rs8973 4.0 interconnection information single-chip sdsl/hdsl transceiver 4.4 crystal/clock interface n8973dsd conexant 4-7 preliminary information 4.4 crystal/clock interface a crystal or an external clock is needed to provide a reference clock for the rs8973. if a crystal is used, it must be connected to the xtali/mclk and xtalo pins along with two external capacitors as shown in figure 4-2 . the recommended specification for the crystal is given in table 4-9 . a list of crystal vendors and their associated part numbers is displayed in table 4-10 . if an external clock is used, it must be connected to the xtali/mclk pin (pin 40), and the xtalo pin (pin 39) must be left floating. the clock frequency must be 10.24 mhz. figure 4-2. crystal oscillator connection diagram table 4-9. crystal specification parameter value nominal frequency 10.24 mhz frequency tolerance at 25 c 10 ppm temperature frequency stability 10 ppm aging 10 ppm over 10 years load capacitance 15.5 pf note(s): individual frequency tolerance, temperature frequency stability, and aging requirements can vary as long as the total tolerance is less than 30 ppm. table 4-10. recommended crystal suppliers supplier name and address supplier phone number part number ecliptek corporation 3545 cadillac avenue costa mesa, ca 92626 (714) 433-1200 ecx-5173-10.240m general electronic devices 320 s. pacific street san marcos, ca 92069 (760) 591-4170 hc49-10.240- .0155- .001/01 22 pf 22 pf y1 xtali / mclk (40) xtal o (39)
4.0 interconnection information rs8973 4.4 crystal/clock interface single-chip sdsl/hdsl transceiver 4-8 conexant n8973dsd preliminary information
n8973dsd conexant 5-1 preliminary information 5 5.0 electrical and mechanical specifications 5.1 absolute maximum ratings stresses above those listed in table 5-1 may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5-1. absolute maximum ratings symbol parameter minimum maximum units v supply supply voltage (1) Cvdd2, vpll, vaa C0.5 +7 v v supply supply voltage (1) Cvdd1 C0.5 4.6 v v i input voltage on any signal pin (2) C0.5 v dd2 + 0.5 v t st storage temperature C65 +125 c t vsol vapor-phase soldering temperature (1 minute) +220 c note(s): (1) v dd1 , v dd2 , relative to dgnd. v aa relative to agnd. (2) relative to dgnd.
5.0 electrical and mechanical specifications rs8973 5.2 recommended operating conditions single-chip sdsl/hdsl transceiver 5-2 conexant n8973dsd preliminary information 5.2 recommended operating conditions the recommended operating conditions are described in table 5-2 . table 5-2. recommended operating conditions symbol parameter minimum typical maximum units v dd1 digital core-logic supply voltage 3.0 3.3 3.6 v v dd2 digital i/o-buffer supply voltage 4.75 5.0 5.25 v v aa analog supply voltage 4.75 5.0 5.25 v v pll pll supply voltage 4.75 5.0 5.25 v v ih high-level input voltage (1) 2.0 v dd2 + 0.3 v v il low-level input voltage C0.3 +0.8 v v ihx high-level input voltage for xtali / mclk 0.9 v dd2 v dd2 + 0.3 v v ilx low-level input voltage for xtali / mclk C0.3 0.1 v dd2 v c l output capacitive loading (2) 60 pf t a ambient operating temperature (3) C40 +85 c (1) v ih (minimum) for the following inputs is 2.2 volts: wr /r/w rbclk rst tbclk (2) capacitive loading over which all digital output switching characteristics are guaranteed. (3) still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaranteed .
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.3 electrical characteristics n8973dsd conexant 5-3 preliminary information 5.3 electrical characteristics typical characteristics measured at nominal operating conditions: ?t a = 25 c ?v dd1 = 3.3 v ?v dd2/aa/pll = 5.0 v minimum/maximum characteristics guaranteed over extreme operating conditions: ? min t a max ? min v dd/aa max the parameters of the electrical characteristics are displayed in table 5-3 .
5.0 electrical and mechanical specifications rs8973 5.3 electrical characteristics single-chip sdsl/hdsl transceiver 5-4 conexant n8973dsd preliminary information table 5-3. electrical characteristics symbol parameter minimum typical maximum units v oh high-level output voltage @ i oh = C 400 m a2.4v v oll low-level output voltage @ i ol = 6 ma (irq and ready )0.4v v ol low-level output voltage @ i ol = 3 ma (all other outputs) 0.4 v i i input leakage current @ v ss2 v i v dd2 10 m a i oz high-impedance output leakage current @ v ss2 v o v dd2 10 m a i pr resistive pull-up current @ v i = v ss2 (tdi and tms) C20 C400 m a i 5v 5 v supply current @ f qclk = 72 khz (1) 100 tbd ma i 5v 5 v supply current @ f qclk = 392 khz (1) 101 tbd ma i 5v 5 v supply current @ f qclk = 584 khz (1) 102 tbd ma i 5v 5 v supply current @ f qclk = 776 khz (1) 103 tbd ma i 5v 5 v supply current @ f qclk = 1160 khz (1) 105 tbd ma i 3v 3.3 v supply current @ f qclk = 72 khz (2) 25tbdma i 3v 3.3 v supply current @ f qclk = 392 khz (2) 54tbdma i 3v 3.3 v supply current @ f qclk = 584 khz (2) 70tbdma i 3v 3.3 v supply current @ f qclk = 776 khz (2) 87tbdma i 3v 3.3 v supply current @ f qclk = 1160 khz (2) 120 tbd ma i pd5v power-down current @ f qclk = 72 khz (3) 15tbdma i pd5v power-down current @ f qclk = 1160 khz (3) 18tbdma i pd3v power-down current @ f qclk = 72 khz (4) 1tbdma i pd3v power-down current @ f qclk = 1160 khz (4) 1tbdma c i input capacitance 10 pf c oz high-impedance output capacitance 10 pf note(s): (1) i 5v = i pll + i dd2 + i aa during normal operation. (2) i 3v = i dd1 during normal operation. (3) i pd5v = i pll + i dd2 + i aa during power-down operation. (4) i pd3v = i dd1 during power-down operation.
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.4 clock timing n8973dsd conexant 5-5 preliminary information 5.4 clock timing tables 5-4 through 5-6 list the clock timing requirements and switching characteristics. figures 5-1 and 5-2 illustrate mclk timing requirements and clock control timing, respectively. table 5-4. mclk timing requirements symbol parameter minimum typical maximum units 1 mclk period (1) 97.653 97.656 97.659 ns 2 mclk pulse-width low 35 ns 3 mclk pulse-width high 35 ns note(s): (1) if an external clock is applied to xtali/mclk, it is referred to as mclk. max tolerance = 32 ppm. edge rates for mclk are < 5 ns. figure 5-1. mclk timing requirements 3 2 1 mclk 8973_014 table 5-5. hclk switching characteristics symbol parameter minimum typical maximum units 4 hclk period (t hclk ), hclk_freq[1:0] = 11 (1) t qclk ? 64 t qclk ? 64 t qclk ? 64 5 hclk period (t hclk ), hclk_freq[1:0] = 00 or 01 (1) t qclk ? 16 t qclk ? 16 t qclk ? 16 6 hclk period (t hclk ), hclk_freq[1:0] = 10 (1) t qclk ? 32 t qclk ? 32 t qclk ? 32 7 hclk pulse-width high t hclk ? 2 C 10 t hclk ? 2t hclk ? 2 + 10 ns 8 hclk pulse-width low t hclk ? 2 C 10 t hclk ? 2t hclk ? 2 + 10 ns note(s): (1) the hclk_freq[1:0] control bits are located in the serial monitor source select register [addr. 0x01].
5.0 electrical and mechanical specifications rs8973 5.4 clock timing single-chip sdsl/hdsl transceiver 5-6 conexant n8973dsd preliminary information table 5-6. qclk switching characteristics symbol parameter minimum maximum units 9 qclk period (t qclk ) (1) 10 qclk pulse-width high t qclk ? 2 C 20 t qclk ? 2 + 20 ns 11 qclk pulse-width low t qclk ? 2 C 20 t qclk ? 2 + 20 ns 12 qclk hold after hclk rising edge C20 ns 13 qclk delay after hclk high 20 ns note(s): (1) t qclk is defined as the time period of the symbol rate. the symbol rate is data rate 2. figure 5-2. clock control timing 4,5,6 11 10 9 7 8 12 13 hclk qclk 8973_015
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.5 channel unit interface timing n8973dsd conexant 5-7 preliminary information 5.5 channel unit interface timing tables 5-7 through 5-12 list channel unit interface timing requirements and switching characteristics. figures 5-3 through 5-5 illustrate channel unit interface timing in parallel master mode, parallel slave mode, and serial mode, respectively. table 5-7. channel unit interface timing requirements, parallel master mode symbol parameter minimum maximum units 14 tq[1,0] setup prior to qclk falling edge 100 ns 15 tq[1,0] hold after qclk low 25 ns table 5-8. channel unit interface switching characteristics, parallel master mode symbol parameter minimum maximum units 16 rq[1,0] hold after qclk rising edge C50 ns 17 rq[1,0] delay after qclk high 50 ns figure 5-3. channel unit interface timing, parallel master mode 14 15 16 17 rq[1,0] qclk tq[1,0] 8973_016
5.0 electrical and mechanical specifications rs8973 5.5 channel unit interface timing single-chip sdsl/hdsl transceiver 5-8 conexant n8973dsd preliminary information table 5-9. channel unit interface timing requirements, parallel slave mode symbol parameter minimum maximum units 18 tbclk, rbclk period (1) t qclk t qclk 19 tbclk , rbclk pulse-width high t qclk ? 4 20 tbclk , rbclk pulse-width low t qclk ? 4 21 tq[1,0] setup prior to tbclk active edge (2) 25 ns 22 tq[1,0] hold after tbclk high/low (2) 25 ns note(s): (1) tbclk and rbclk must be frequency-locked to qclk, though they may have independent phase relationships to qclk and to one another. (2) tbclk polarity (edge sensitivity) is programmable through the cu interface modes register [cu_interface_modes 0x06]. table 5-10. channel unit interface switching characteristics, parallel slave mode symbol parameter minimum maximum units 23 rq[1,0] hold after rbclk active edge (1) 0ns 24 rq[1,0] delay after rbclk high/low (1) 100ns note(s): (1) rbclk polarity (edge sensitivity) is programmable through the cu interface modes register [cu_interface_modes; 0x06]. figure 5-4. channel unit interface timing, parallel slave mode rq[1:0] tbclk tq[1:0] rbclk 18 19 20 21 23 24 18 19 20 22 8973_017
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.5 channel unit interface timing n8973dsd conexant 5-9 preliminary information note(s): tbclk and rbclk polarities are programmable through the cu interface modes register. the figure depicts both clocks programmed to falling-edge active. figure 5-4. channel unit interface timing, parallel slave mode table 5-11. channel unit interface timing requirements, serial mode symbol parameter minimum maximum units 25 tdat setup prior to bclk falling edge 100 ns 26 tdat hold after bclk low 25 ns table 5-12. channel unit interface switching characteristics, serial mode symbol parameter minimum maximum units 27 bclk period t qclk ? 2t qclk ? 2 28 bclk pulse-width high t qclk ? 4 C 20 t qclk ? 4 + 20 ns 29 bclk pulse-width low t qclk ? 4 C 20 t qclk ? 4 + 20 ns 30 bclk hold after hclk rising edge 0 ns 31 bclk delay after hclk high 50 ns 32 rdat, qclk hold after bclk rising edge C50 ns 33 rdat, qclk delay after bclk high 50 ns
5.0 electrical and mechanical specifications rs8973 5.5 channel unit interface timing single-chip sdsl/hdsl transceiver 5-10 conexant n8973dsd preliminary information figure 5-5. channel unit interface timing, serial mode hclk bclk tdat qclk rdat 25 27 28 29 30 31 32 33 26 8973_018
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.6 microcomputer interface timing n8973dsd conexant 5-11 preliminary information 5.6 microcomputer interface timing tables 5-13 and 5-14 list microcomputer interface (mci) timing requirements and switching characteristics, respectively. figures 5-6 through 5-9 illustrate mci write and read timing. figure 5-10 illustrates internal write timing. table 5-13. microcomputer interface timing requirements symbol parameter minimum maximum units 34 ale pulse-width high 30 ns 35 address setup prior to ale falling edge (1) 10 ns 36 address hold after ale low (1) 5ns 37 ale low prior to write strobe falling edge (2) 20 ns 38a read strobe falling edge after ale falling edge C muxed mode (muxed = 1) (3) 20 ns 38b read strobe falling edge after ale falling edge C non-muxed mode (muxed = 0) (3) 1ns 39 write strobe pulse-width low (2,4) t qclk 32 + 25 ns 40 read strobe pulse-width low (3,4) t qclk 32 + 25 ns 41 data in setup prior to write strobe rising edge (2) 30 ns 42 data in hold after write strobe high (2) 5ns 43 r/w setup prior to read/write strobe falling edge 10 ns 44 r/w hold after read/write strobe high 10 ns 45 ale falling edge after write strobe high 20 ns 46 ale falling edge after read strobe high 20 ns 47 rst pulse-width low 50 ns 48 write strobe rising edge after ready low 0 ns note(s): (1) address is defined as ad[7:0] when muxed = 1, and addr[7:0] when muxed = 0. (2) in intel mode, write strobe is defined as wr and cs asserted. in motorola mode, it is defined as ds and cs asserted when r/w is low. (3) in intel mode, read strobe is defined as rd and cs asserted. in motorola mode, it is defined as ds and cs asserted when r/w is high. (4) the timing listed is for the synchronous mode of the mci, which is power-on default. it can also be set to asynchronous mode by setting bit 0 of the miscellaneous/test register (address 0x0f) to a 1. in this case, the minimum timing changes to 40 ns fo r symbol 39, and 50 ns for symbols 40 and 50. synchronous mode is preferred because it reduces switching noise. to switch to asynchronous mode, the write strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a symbol rate of 640 kbps (74 nx), which is the power-on default.
5.0 electrical and mechanical specifications rs8973 5.6 microcomputer interface timing single-chip sdsl/hdsl transceiver 5-12 conexant n8973dsd preliminary information table 5-14. microcomputer interface switching characteristics symbol parameter minimum maximum units 49 data out enable (low z) after read strobe falling edge (1) 2ns 50 data out valid after read strobe low (1, 7) t qclk 32 + 25 ns 51 data out hold after read strobe rising edge (1) 2ns 52 data out disable (high z) after read strobe high (1) 25ns 53 irq hold after write strobe rising edge (2,3) 5ns 54 irq delay after write strobe high (2,3) t qclk 32 + 20 ns 55 internal register delay after write strobe high (3,4) t qclk 32 ns 56 internal ram delay after write strobe high (3,5) 2 t qclk ns 57 access data register delay after write strobe high (3,6) 2 t qclk ns 58 ready low after write strobe low (3) 0t qclk 32 ns 59 ready rising edge after write strobe high (3) 050ns 60 ready low after read strobe low (1) 0t qclk 32 ns 61 ready rising edge after read strobe high (1) 050ns 62 data out valid after ready low 10 ns note(s): (1) read strobe is defined as rd and cs asserted in intel mode, and ds and cs asserted when r/w is high in motorola mode. (2) when writing an interrupt mask or status register. (3) write strobe is defined as wr and cs asserted in intel mode, and ds and cs asserted when r/w is low in motorola mode. (4) writes to internal registers are synchronized to an internal 64-times symbol-rate clock. data is available for reading after the specified time. this parameter may extend the overall read access time from internal register locations under high bus speed/low symbol rate conditions. (5) when performing an indirect write to ram-based locations using a write select register [odd addresses: 0x71C0x7b] and the access data register. subsequent writes to any read/write select register or the access data register, as initiated by a write strobe falling edge, is prohibited for the specified time. this parameter will extend the overall write access time to ram-based locations under normal bus speed/symbol rate conditions. (6) when performing an indirect read from ram-based locations using a read select register [even addresses: 0x70C0x7a] and the access data register. subsequent writes to any read/write select register, as initiated by a write strobe falling-edge, is prohibited for the specified time. data is available for reading from the access data register after the specified time. this parameter will extend the overall read access time from ram-based locations under normal bus speed/symbol rate conditions. direct writes to the access data register are as specified for internal registers. (7) the timing listed is for the synchronous mode of the mci, which is power-on default. it can also be set to asynchronous mode by setting bit 0 of the reserved9 register (address 0x0f) to a 1. in this case, the minimum timing changes to 40 ns for symbol 39, and 50 ns for symbols 40 and 50. synchronous mode is preferred because it reduces switching noise. to switch to asynchronous mode, the write strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a symbol rate of 640 kbps (74 nx), which is the power-on default.
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.6 microcomputer interface timing n8973dsd conexant 5-13 preliminary information figure 5-6. mci write timing, intel mode (motel = 0) write strobe ale 35 36 37 34 39 41 42 address data (input) 45 ad[7:0] or addr[7:0] ready 58 59 48 8973_019
5.0 electrical and mechanical specifications rs8973 5.6 microcomputer interface timing single-chip sdsl/hdsl transceiver 5-14 conexant n8973dsd preliminary information figure 5-7. mci write timing, motorola mode (motel = 1) ad[7:0] write strobe ale 35 36 37 34 39 41 42 r/w 43 address data (input) 45 58 59 or addr[7:0] ready 48 44 8973_020 figure 5-8. mci read timing, intel mode (motel = 0) read strobe ale 35 36 34 40 51 address data (output) 49 50 52 46 ad[7:0] or addr[7:0] 38 ready 61 60 62 8973_021
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.6 microcomputer interface timing n8973dsd conexant 5-15 preliminary information figure 5-9. mci read timing, motorola mode (motel = 1) read strobe ale 35 36 34 40 51 address data (output) 49 50 52 r/w 43 44 46 ad[7:0] or addr[7:0] 38 ready 61 60 62 8973_022
5.0 electrical and mechanical specifications rs8973 5.6 microcomputer interface timing single-chip sdsl/hdsl transceiver 5-16 conexant n8973dsd preliminary information figure 5-10. internal write timing irq write 53 54 strobe 55 56 internal register internal ram access data register 57 8973_023
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.7 test and diagnostic interface timing n8973dsd conexant 5-17 preliminary information 5.7 test and diagnostic interface timing tables 5-15 and 5-16 list test and diagnostic interface timing requirements and switching characteristics. figures 5-11 and 5-12 illustrate jtag interface and smon timing, respectively. table 5-15. test and diagnostic interface timing requirements symbol parameter minimum maximum units 63 tck pulse-width high 80 ns 64 tck pulse-width low 80 ns 65 tms, tdi setup prior to tck rising edge (1) 20 ns 66 tms, tdi hold after tck high (1) 20 ns note(s): (1) also applies to functional inputs for sample/preload and extest instructions.
5.0 electrical and mechanical specifications rs8973 5.7 test and diagnostic interface timing single-chip sdsl/hdsl transceiver 5-18 conexant n8973dsd preliminary information table 5-16. test and diagnostic interface switching characteristics symbol parameter minimum maximum units 67 tdo hold after tck falling edge (1) 0ns 68 tdo delay after tck low (1) 50ns 69 tdo enable (low z) after tck falling edge (1) 2ns 70 tdo disable (high z) after tck low (1) 25ns 71 smon hold after hclk rising edge (2) 0ns 72 smon delay after hclk high (2) 50ns note(s): (1) also applies to functional outputs for the extest instruction. (2) hclk must be programmed to operate at 16 times the symbol rate (16 f qclk ). figure 5-11. jtag interface timing 63 64 65 66 67 68 69 70 tdo tck tdi tms 8973_024 figure 5-12. smon timing 71 72 hclk smon 8973_025
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.8 analog specifications n8973dsd conexant 5-19 preliminary information 5.8 analog specifications tables 5-17 and 5-18 list transmitter and receiver analog requirements and specifications. figure 5-13 and table 5-19 show the transmit pulse template for two- and three-pair systems. figure 5-14 and table 5-20 show the transmit pulse template for one-pair systems. figures 5-15 through 5-17 illustrate the upper bound of the average psd of 392, 584, and 1160 kbaud systems, respectively. table 5-17. receiver requirements and specifications parameter comments min typ max unit s input signals rxp, rxn, rxbp, and rxbn input voltage range with respect to vaa/2 C2.25 +2.25 v input resistance @ data rate = 2320 kbps 10 k w input resistance @ data rate = 144 kbps 35 k w common mode voltage vcomi vaa 0.4 v vga six gains from 0 db to +15 db gain step 2.55 3.0 3.42 db adc differential voltage range (full scale input, fs) (1) (v rxp C v rxn )(v rxbp C v rxbn ) 5.4 6.0 6.6 v p timing recovery pll pull-in range (digital) 64 ppm pll settling time 10 ms note(s): (1) corresponds to the voltages that produce a full scale reading from the adc when the vga gain equals o db. the input voltage range is reduced proportionally as vga gain is increased. table 5-18. transmitter analog requirements and specifications (1 of 2) parameter comments min typ max units transmit symbol rate (f qclk ) qclk frequency (data rate/2) 72 1160 khz pulse template (1, 2, 3) see figure 5-13 and figure 5-14 , r l = 135 w
5.0 electrical and mechanical specifications rs8973 5.8 analog specifications single-chip sdsl/hdsl transceiver 5-20 conexant n8973dsd preliminary information power spectral density (1, 2, 3,4) see figures 5-15 , 5-16 and 5-17 , r l = 135 w average power (1, 2, 3,4) dc to 2 x f qclk , r l = 135 w , calibrated gain setting 13.4 14 dbm gain adjustment step controlled by transmit gain register [0x29] 0.20 db common-mode voltage vcomo vaa/2 v output impedance (1) dc to 1 mhz 2 w note(s): (1) guaranteed by design and characterization. (2) see figure 5-18 of section 5.9, test conditions , for the test circuit. (3) measured after the transmitter is calibrated by writing the value in the transmitter calibration register [tx_calibrate; 0x2 8] to the transmitter gain register [tx_gain; 0x29]. (4) measured with a pseudo-random code sequence of pulses. table 5-18. transmitter analog requirements and specifications (2 of 2) parameter comments min typ max units figure 5-13. transmit pulse template for two- and three-pair systems; normalized pulse mask (source etsi ts 101 135 formerly etr 152) C 0,4t 0,4t b = 1,07 c = 1,00 d = 0,93 C 1,2t a = 0,01 f = C 0,01 0t C 0,6t 14t 50t 0,5t 1,25t g = C 0,16 e = 0,03 a = 0,01 f = C 0,01 h = C 0,05 t = 2,55 m s at 784 kbps t = 1,71 m s at 1168 kbps 8973_026
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.8 analog specifications n8973dsd conexant 5-21 preliminary information table 5-19. transmit pulse template for two- and three-pair systems (source etsi ts 101 135 formerly etr 152) normalized level quaternary symbols + 3 + 1 C 1 C 3 a 0.01 0.0264 0.0088 C0.0088 C0.0264 b 1.07 2.8248 0.9416 C0.9416 C2.8248 c 1.00 2.6400 0.8800 C0.8800 C2.6400 d 0.93 2.4552 0.8184 C0.8184 C2.4552 e 0.03 0.0792 0.0264 C0.0264 C0.0792 f C0.01 C0.0264 C0.0088 0.0088 0.0264 g C0.16 C0.4224 C0.1408 0.1408 0.4224 h C0.05 C0.1320 C0.0440 0.0440 0.1320
5.0 electrical and mechanical specifications rs8973 5.8 analog specifications single-chip sdsl/hdsl transceiver 5-22 conexant n8973dsd preliminary information figure 5-14. transmit pulse template for one-pair systems (source etsi ts 101 135 formerly etr 152) C 0,4t 0,4t b = 1,07 c = 1,00 d = 0,93 C 1,2t a = 0,01 f = C 0,01 0t C 0,6t 14t 50t 0,5t 1,25t g = C 0,20 e = 0,04 a = 0,01 f = C 0,01 h = C 0,05 t = 0,862 m s at 2320 kbps 8973_027 table 5-20. transmit pulse template for one-pair systems (source etsi ts 101 135 formerly etr 152) normalized level quaternary symbols + 3 + 1 C 1 C 3 a 0.01 0.0250 v 0.0083 v C0.0083 v C0.0250 v b 1.07 2.6750 v 0.8917 v C0.8917 v C2.6750 v c 1.00 2.500 v 0.8333 v C0.8333 v C2.5000 v d 0.93 2.3250 v 0.7750 v C0.7750 v C2.3250 v e 0.04 0.1000 v 0.0333 v C0.0333 v C0.1000 v f C0.01 C0.0250 v C0.0083 v 0.0083 v 0.0250 v g C0.20 C0.5000 v C0.1667 v 0.1667 v 0.5000 v h C0.05 C0.1250 v C0.0417 v 0.0417 v 0.1250 v
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.8 analog specifications n8973dsd conexant 5-23 preliminary information figure 5-15. upper bound of the average psd of a 392 kbaud system (source etsi ts 101 135 formerly etr 152) C 20 C 40 C 60 C 80 C 100 C 120 11 1 14 1,96 1,96 e3 e4 e5 e5 e6 e6 e6 hz dbm/hz C 37 dbm/hz floor at C 117 dbm/hz 8973_028 figure 5-16. upper bound of the average psd of a 584 kbaud system (source etsi ts 101 135 formerly etr 152) C 20 C 40 C 60 C 80 C 100 C 120 11 1 14 2,92 2,92 e3 e4 e5 e5 e6 e6 e6 hz dbm/hz C 39 dbm/hz floor at C 119 dbm/hz 8973_029
5.0 electrical and mechanical specifications rs8973 5.9 test conditions single-chip sdsl/hdsl transceiver 5-24 conexant n8973dsd preliminary information 5.9 test conditions figure 5-18 shows the transmitter test circuit. figures 5-19 and 5-20 show the standard output and open-drain output loads, respectively. figure 5-17. upper bound of the average psd of a 1160 kbaud system (source etsi ts 101 135 formerly etr 152) C 20 C 40 C 60 C 80 C 100 C 120 C 130 11 1 11 4,85 4,85 e3 e4 e5 e5 e6 e6 e7 hz dbm/hz C 41,5 dbm/hz floor at C 121,5 dbm/hz 8973_030 figure 5-18. transmitter test circuit txp (71) + C line transformer + C r l 1:2 + C 15.4 w 15.4 w primary inductance = 2mh line driver rs8973 8973_031 txp (74)
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.9 test conditions n8973dsd conexant 5-25 preliminary information figure 5-19. standard output load (totem pole and three-state outputs) figure 5-20. open-drain output load (irq ) 8973_032 cl from rs8973 iol ioh 1.5 v 8973_033 c l from rs8973 i od v dd2
5.0 electrical and mechanical specifications rs8973 5.10 timing measurements single-chip sdsl/hdsl transceiver 5-26 conexant n8973dsd preliminary information 5.10 timing measurements figure 5-21 shows the input waveforms. figures 5-22 and 5-23 show the output waveforms. figure 5-21. input waveforms for timing tests 3 v 0 v 2.0 v 0.8 v input high input low input high input low 8973_034 figure 5-22. output waveforms for timing tests ? vdd ? 0 v 2.4 v 0.4 v output high output low output high output low 8973_035
rs8973 5.0 electrical and mechanical specifications single-chip sdsl/hdsl transceiver 5.10 timing measurements n8973dsd conexant 5-27 preliminary information figure 5-23. output waveforms for three-state enable and disable tests 1.7 v 1.3 v output disabled output enabled 1.5 v 8973_036 v oh C 0.2 v v ol + 0.2 v output disabled
5.0 electrical and mechanical specifications rs8973 5.11 mechanical specifications single-chip sdsl/hdsl transceiver 5-28 conexant n8973dsd preliminary information 5.11 mechanical specifications figure 5-24. 100-pin pqfp top view bottom view d e e1 d1 b e a a2 a1 l 1.60 (.063) ref. all dimensions in millimeters s y m b o l a a 1 a 2 d d 1 e e 1 l e b min. ---- 0.25 2.57 0.65 0.22 max. 3.40 ---- 2.87 0.95 0.38 nom. 3.04 0.33 2.71 23.20 bsc. 20.00 bsc. 17.20 bsc. 14.00 bsc. 0.70 0.65 bsc. ---- 8973_037
n8973dsd conexant a-1 preliminary information a appendix a: acronym list the following list of acronyms and abbreviations does not include all signal, register, and bit names. a adc analog-to-digital converter agc automatic gain control b bdsl boundary scan description language ber bit error rate 2b1q two binary, one quaternary encoding/decoding scheme c cot central office terminal ct continuous time d dac digital-to-analog converter dagc digital automatic gain control dfe decision feedback equalizer dsp digital signal processor e ec echo canceller ep error predictor etsi european telecommunications standard institute f felm far-end level meter ffe feed forward equalizer fir finite impulse response h hdsl high-bit-rate digital subscriber line i ic integrated circuit is impulse shortening
appendix a : acronym list rs8973 single-chip sdsl/hdsl transceiver a-2 conexant n8973dsd preliminary information j jtag joint test action group l lec linear echo canceller lms least mean square lsb least significant bit m mci microcomputer interface msb most significant bit n nec nonlinear echo canceller p pcb printed circuit board pkd peak detector pll phase lock loop pqfp plastic quad flat pack psd power spectral density q quat quaternary r rt remote terminal s sdsl symmetric digital subscriber line over single pair slm signal level meter smon serial monitor snr signal-to-noise ratio t tap test access port tck test clock tms test mode select v vga variable gain amplifier x xo crystal oscillator
further information literature@c onexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road p. o. box c newport beach, ca 92658-8902 phone: (949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: (215) 244-6784 fax: (215) 244-9292 u.s. north central phone: (630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: (978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: (408) 249-9696 fax: (408) 249-7113 u . s. south central phone: (972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: (919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: (949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: (852) 2827 0181 fax: (852) 2827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 phone: (82 53) 745 2880 fax: (82 53) 745 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 4) 93 00 33 35 fax:(334)93003303 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax:(331)41443690 middle east headquarters conexant systems commercial (israel) ltd. p. o. box 12660 herzlia 46733, israel phone: (972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371-1567 fax: (81 3) 5371-1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: (886 2) 2720 0282 fax: (886 2) 2757 6760 0.0 sales offices

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